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| author | Nicholas Piggin <npiggin@gmail.com> | 2017-04-06 01:33:20 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-04-07 14:10:32 +1000 |
| commit | 5e738d586828f9ac1c2421f46a8c883606088162 (patch) | |
| tree | 5646823da983fba9911cd3384de6d07a88e39f7b | |
| parent | 0adcaba138fc146ea746a758814b9e487c8caee6 (diff) | |
| download | skiboot-5e738d586828f9ac1c2421f46a8c883606088162.zip skiboot-5e738d586828f9ac1c2421f46a8c883606088162.tar.gz skiboot-5e738d586828f9ac1c2421f46a8c883606088162.tar.bz2 | |
asm: do not set SDR1 on POWER9
This register does not exist in ISAv3.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | asm/head.S | 4 |
1 files changed, 3 insertions, 1 deletions
@@ -655,7 +655,6 @@ cleanup_tlb: .global init_shared_sprs init_shared_sprs: li %r0,0 - mtspr SPR_SDR1, %r0 mtspr SPR_AMOR, %r0 mfspr %r3,SPR_PVR @@ -676,18 +675,21 @@ init_shared_sprs: b 9f 1: /* P7 */ + mtspr SPR_SDR1, %r0 /* TSCR: Value from pHyp */ LOAD_IMM32(%r3,0x880DE880) mtspr SPR_TSCR, %r3 b 9f 2: /* P7+ */ + mtspr SPR_SDR1, %r0 /* TSCR: Recommended value by HW folks */ LOAD_IMM32(%r3,0x88CDE880) mtspr SPR_TSCR, %r3 b 9f 3: /* P8E/P8 */ + mtspr SPR_SDR1, %r0 /* TSCR: Recommended value by HW folks */ LOAD_IMM32(%r3,0x8ACC6880) mtspr SPR_TSCR, %r3 |