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authorVasant Hegde <hegdevasant@linux.vnet.ibm.com>2020-04-07 19:47:34 +0530
committerOliver O'Halloran <oohall@gmail.com>2020-04-15 14:05:53 +1000
commit346647465ab3f3b78c6729857fe3bee2d70ee0cd (patch)
treeb973d5d70024cbfadf561e5efae7a688fe7329ab
parentd6eb510d65e6a9d5bd69b6960c08d165f8363de3 (diff)
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MPIPL: Add support to save crash CPU details on FSP system
OPAL uses different path to trigger MPIPL: - On BMC system we call SBE S0 interrupt - On FSP system we call `attn` instruction Currently on BMC system we collect crash CPU PIR details.. which is needed to generate proper dump. This happens just before calling SBE S0 interrupt. Since we don't use this path in FSP system OPAL is not saving crashing CPU details. Hence by default `opalcore` is not pointing to crashing CPU and not showing proper backtrace. We have to go through all CPUs to find crashing CPU backtrace. This patch move this function to common place so that if MPIPL is supported we collect crashing CPU data. Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com> Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
-rw-r--r--core/opal-dump.c9
-rw-r--r--core/utils.c4
-rw-r--r--hw/sbe-p9.c3
3 files changed, 13 insertions, 3 deletions
diff --git a/core/opal-dump.c b/core/opal-dump.c
index 639946c..a31ecbe 100644
--- a/core/opal-dump.c
+++ b/core/opal-dump.c
@@ -487,6 +487,15 @@ static void post_mpipl_get_opal_data(void)
void opal_mpipl_save_crashing_pir(void)
{
+ struct dt_node *opal_node;
+
+ opal_node = dt_find_by_path(dt_root, "ibm,opal");
+ if (!opal_node)
+ return;
+
+ if (!dt_find_by_path(opal_node, "dump"))
+ return;
+
mpipl_metadata->crashing_pir = this_cpu()->pir;
prlog(PR_NOTICE, "Crashing PIR = 0x%x\n", this_cpu()->pir);
}
diff --git a/core/utils.c b/core/utils.c
index 0d2f5e8..d778fcd 100644
--- a/core/utils.c
+++ b/core/utils.c
@@ -12,6 +12,7 @@
#include <processor.h>
#include <cpu.h>
#include <stack.h>
+#include <opal-dump.h>
void __noreturn assert_fail(const char *msg, const char *file,
unsigned int line, const char *function)
@@ -33,6 +34,9 @@ void __noreturn assert_fail(const char *msg, const char *file,
prlog(PR_EMERG, "assert failed at %s:%u: %s\n", file, line, msg);
backtrace();
+ /* Save crashing CPU details */
+ opal_mpipl_save_crashing_pir();
+
if (platform.terminate)
platform.terminate(msg);
diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c
index 31f8cb9..18caa0a 100644
--- a/hw/sbe-p9.c
+++ b/hw/sbe-p9.c
@@ -958,9 +958,6 @@ void p9_sbe_terminate(void)
return;
}
- /* Save crashing CPU details */
- opal_mpipl_save_crashing_pir();
-
/*
* Send S0 interrupt to all SBE. Sequence:
* - S0 interrupt on secondary chip SBE