diff options
author | Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com> | 2017-08-17 17:50:24 -0700 |
---|---|---|
committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-21 11:58:19 +1000 |
commit | b503dcf16d28f75f145f022c3e9c0ca97dd240e0 (patch) | |
tree | 768afd11e63fe439dc03885b66565a23eb6ba3e6 | |
parent | ec5065a07cd465f85cf2614919c140a5cf61dd56 (diff) | |
download | skiboot-b503dcf16d28f75f145f022c3e9c0ca97dd240e0.zip skiboot-b503dcf16d28f75f145f022c3e9c0ca97dd240e0.tar.gz skiboot-b503dcf16d28f75f145f022c3e9c0ca97dd240e0.tar.bz2 |
vas: Set mmio enable bits in DD2
POWER9 DD2 added some new "enable" bits that must be set for VAS to
work. These bits were unused in DD1.
Signed-off-by: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Acked-By: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
-rw-r--r-- | core/vas.c | 3 | ||||
-rw-r--r-- | include/vas.h | 3 |
2 files changed, 6 insertions, 0 deletions
@@ -103,6 +103,9 @@ static int init_north_ctl(struct proc_chip *chip) val = SETFIELD(VAS_64K_MODE_MASK, val, true); val = SETFIELD(VAS_ACCEPT_PASTE_MASK, val, true); + val = SETFIELD(VAS_ENABLE_WC_MMIO_BAR, val, true); + val = SETFIELD(VAS_ENABLE_UWC_MMIO_BAR, val, true); + val = SETFIELD(VAS_ENABLE_RMA_MMIO_BAR, val, true); return vas_scom_write(chip, VAS_MISC_N_CTL, val); } diff --git a/include/vas.h b/include/vas.h index da19645..bc0aff7 100644 --- a/include/vas.h +++ b/include/vas.h @@ -131,6 +131,9 @@ extern __attrconst uint64_t vas_get_wcbs_bar(int chipid); #define VAS_64K_MODE_MASK PPC_BIT(0) #define VAS_ACCEPT_PASTE_MASK PPC_BIT(1) #define VAS_QUIESCE_REQ_MASK PPC_BIT(4) +#define VAS_ENABLE_WC_MMIO_BAR PPC_BIT(6) +#define VAS_ENABLE_UWC_MMIO_BAR PPC_BIT(7) +#define VAS_ENABLE_RMA_MMIO_BAR PPC_BIT(8) #define VAS_HMI_ACTIVE_MASK PPC_BIT(58) #define VAS_RG_IDLE_MASK PPC_BIT(59) |