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| author | Stewart Smith <stewart@linux.ibm.com> | 2019-06-05 11:35:13 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-06-07 13:59:42 +1000 |
| commit | db3929ee4f0a98596938f05da2789686908ebfd4 (patch) | |
| tree | 503fd4f75d118c181948d4a5e131c4c6f986a0b4 | |
| parent | 0a2f8fbf931491ed97c1d11a5ae85b9d30338162 (diff) | |
| download | skiboot-db3929ee4f0a98596938f05da2789686908ebfd4.zip skiboot-db3929ee4f0a98596938f05da2789686908ebfd4.tar.gz skiboot-db3929ee4f0a98596938f05da2789686908ebfd4.tar.bz2 | |
doc: Futher document OPAL_REINIT_CPUS_MMU_* modes
Fixes: https://github.com/open-power/skiboot/issues/134
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
| -rw-r--r-- | doc/opal-api/opal-reinit-cpus-70.rst | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/doc/opal-api/opal-reinit-cpus-70.rst b/doc/opal-api/opal-reinit-cpus-70.rst index 2522e76..3a6e543 100644 --- a/doc/opal-api/opal-reinit-cpus-70.rst +++ b/doc/opal-api/opal-reinit-cpus-70.rst @@ -44,6 +44,20 @@ OPAL_REINIT_CPUS_TM_SUSPEND_DISABLED This flag requests that CPUs be configured with TM (Transactional Memory) suspend mode disabled. This may only be supported on some CPU versions. +OPAL_REINIT_CPUS_MMU_HASH and OPAL_REINIT_CPUS_MMU_RADIX +^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ + +Some processors may need to change a processor specific register in order to +support Hash or Radix translation. + +For POWER9 CPUs, this is bit 8 of the HID register (see the POWER9 User Manual +for details). On POWER9 CPUS, when in Hash mode, the full TLB is available to +the host OS rather than when in radix mode, half the TLB is taken for a Page +Walk Cache (PWC). + +Future CPUs may or may not do anything with these flags, but a host OS must +use them to ensure compatibility in the future. + Returns ------- |