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| author | Ananth N Mavinakayanahalli <ananth@in.ibm.com> | 2015-11-06 15:10:44 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-11-12 16:05:23 +1100 |
| commit | 42d5d04758b4aa30e83e741a489f25592d4ad896 (patch) | |
| tree | f9209af79dff247250eecc7510a471b02071e18e | |
| parent | fff572c0bbad746c477d733fbde5280667d931f8 (diff) | |
| download | skiboot-42d5d04758b4aa30e83e741a489f25592d4ad896.zip skiboot-42d5d04758b4aa30e83e741a489f25592d4ad896.tar.gz skiboot-42d5d04758b4aa30e83e741a489f25592d4ad896.tar.bz2 | |
FSP: Handle DPO initiated CEC shutdown with FSP in RR
In a scenario where the DPO has been initiated, but the FSP then went into
reset before the CEC power down came in, OPAL may not give up the link since
it may never see the PSI interrupt. So, if we are in dpo_pending and an FSP
reset is detected via the DISR, give up the PSI link voluntarily.
Tested-by: Vipin K Parashar <vipin@linux.vnet.ibm.com>
Signed-off-by: Ananth N Mavinakayanahalli <ananth@in.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/fsp/fsp-dpo.c | 2 | ||||
| -rw-r--r-- | hw/fsp/fsp.c | 20 | ||||
| -rw-r--r-- | include/fsp.h | 1 |
3 files changed, 19 insertions, 4 deletions
diff --git a/hw/fsp/fsp-dpo.c b/hw/fsp/fsp-dpo.c index 51c4824..8e88d8f 100644 --- a/hw/fsp/fsp-dpo.c +++ b/hw/fsp/fsp-dpo.c @@ -30,7 +30,7 @@ #define DPO_CMD_SGN_BYTE1 0x20 /* Byte[1] signature */ #define DPO_TIMEOUT 2700 /* 45 minutes in seconds */ -static bool fsp_dpo_pending = false; +bool fsp_dpo_pending = false; static unsigned long fsp_dpo_init_tb = 0; /* diff --git a/hw/fsp/fsp.c b/hw/fsp/fsp.c index ab625a5..b53c3f0 100644 --- a/hw/fsp/fsp.c +++ b/hw/fsp/fsp.c @@ -666,9 +666,23 @@ static void fsp_handle_errors(struct fsp *fsp) if (fsp->state == fsp_mbx_rr) return; - prlog(PR_NOTICE, "FSP #%d: FSP in Reset." - " Waiting for PSI interrupt\n", - fsp->index); + if (fsp_dpo_pending) { + /* + * If we are about to process a reset when DPO + * is pending, its possible that the host has + * gone down, and OPAL is on its way down and + * hence will not see the subsequent PSI interrupt. + * So, just give up the link here. + */ + prlog(PR_NOTICE, "FSP #%d: FSP reset with DPO pending." + " Giving up PSI link\n", + fsp->index); + psi_disable_link(psi); + } else { + prlog(PR_NOTICE, "FSP #%d: FSP in Reset." + " Waiting for PSI interrupt\n", + fsp->index); + } fsp_start_rr(fsp); } diff --git a/include/fsp.h b/include/fsp.h index 4e247cc..a61bd58 100644 --- a/include/fsp.h +++ b/include/fsp.h @@ -823,6 +823,7 @@ extern void fsp_epow_init(void); /* DPO */ extern void fsp_dpo_init(void); +extern bool fsp_dpo_pending; /* Chiptod */ extern void fsp_chiptod_init(void); |