diff options
| author | Oliver O'Halloran <oohall@gmail.com> | 2019-08-02 18:00:03 +1000 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2019-10-03 12:56:57 +0530 |
| commit | 6d6f05db61c7c757ab5c818b34dd159f3e69b664 (patch) | |
| tree | 297654be8ccec42cc29c4b2031b0fbf1481aa572 | |
| parent | 5445f9cd2683cf52a6d091d8d3ff74ed498454e4 (diff) | |
| download | skiboot-6d6f05db61c7c757ab5c818b34dd159f3e69b664.zip skiboot-6d6f05db61c7c757ab5c818b34dd159f3e69b664.tar.gz skiboot-6d6f05db61c7c757ab5c818b34dd159f3e69b664.tar.bz2 | |
hw/phb4: Prevent register accesses when in reset
[ Upstream commit b310e8f79e6817e18bd0e3c606da50a00b425ef0 ]
While the the ETU is in reset we cannot access any of the PHB registers.
If a PHB register is accessed via the XSCOM indirect interface then
we'll cause an ETU reset error which may prevent the PHB from being
re-initialised once the reset is lifted.
Prevent register accesses while in reset by adding a flag that is set
while the ETU reset bit is high and checking that flag in the XSCOM
(ASB) backdoor register access path.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 10 | ||||
| -rw-r--r-- | include/phb4.h | 1 |
2 files changed, 11 insertions, 0 deletions
@@ -225,6 +225,10 @@ static inline void phb4_write_reg_asb(struct phb4 *p, static uint64_t phb4_read_reg(struct phb4 *p, uint32_t offset) { + /* No register accesses are permitted while in reset */ + if (p->flags & PHB4_ETU_IN_RESET) + return -1ull; + if (p->flags & PHB4_CFG_USE_ASB) return phb4_read_reg_asb(p, offset); else @@ -233,6 +237,10 @@ static uint64_t phb4_read_reg(struct phb4 *p, uint32_t offset) static void phb4_write_reg(struct phb4 *p, uint32_t offset, uint64_t val) { + /* No register accesses are permitted while in reset */ + if (p->flags & PHB4_ETU_IN_RESET) + return; + if (p->flags & PHB4_CFG_USE_ASB) phb4_write_reg_asb(p, offset, val); else @@ -3268,6 +3276,7 @@ static int64_t phb4_creset(struct pci_slot *slot) phb4_err_clear(p); /* Actual reset */ + p->flags |= PHB4_ETU_IN_RESET; xscom_write(p->chip_id, p->pci_stk_xscom + XPEC_PCI_STK_ETU_RESET, 0x8000000000000000UL); @@ -3321,6 +3330,7 @@ static int64_t phb4_creset(struct pci_slot *slot) /* Clear PHB from reset */ xscom_write(p->chip_id, p->pci_stk_xscom + XPEC_PCI_STK_ETU_RESET, 0x0); + p->flags &= ~PHB4_ETU_IN_RESET; pci_slot_set_state(slot, PHB4_SLOT_CRESET_REINIT); /* After lifting PHB reset, wait while logic settles */ diff --git a/include/phb4.h b/include/phb4.h index c52a840..dc84fca 100644 --- a/include/phb4.h +++ b/include/phb4.h @@ -166,6 +166,7 @@ struct phb4_err { #define PHB4_CFG_BLOCKED 0x00000004 #define PHB4_CAPP_RECOVERY 0x00000008 #define PHB4_CAPP_DISABLE 0x00000010 +#define PHB4_ETU_IN_RESET 0x00000020 struct phb4 { unsigned int index; /* 0..5 index inside p9 */ |