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| author | Jordan Niethe <jniethe5@gmail.com> | 2019-08-08 15:37:32 +1000 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2019-10-03 12:02:31 +0530 |
| commit | 211a1e042a298aab78a771f570e47164b6d8c2ca (patch) | |
| tree | 7b7776f4d3693fb71b243048005a541428e3919f | |
| parent | 0ea10b2b6115d4be8559b79c1e90abae539476e3 (diff) | |
| download | skiboot-211a1e042a298aab78a771f570e47164b6d8c2ca.zip skiboot-211a1e042a298aab78a771f570e47164b6d8c2ca.tar.gz skiboot-211a1e042a298aab78a771f570e47164b6d8c2ca.tar.bz2 | |
hw/phb4: Use standard MIN/MAX macro definitions
[ Upstream commit 41f6c806091627dff980d6d0d96f04f19517394d ]
The max() macro definition incorrectly returns the minimum value. The
max() macro is used to ensure that PERST has been asserted for 250ms and
that we wait 100ms seconds for the ETU logic in the CRESET_START PHB4
PCI slot state. However, by returning the minimum value there is no
guarantee that either of these requirements are met.
Correct macro definitions for MIN and MAX are already provided in
skiboot.h. Remove the redundant/incorrect versions here and switch to
using the standard ones.
Fixes: 70edcbb4b39d ("hw/phb4: Skip FRESET PERST when coming from
CRESET")
Signed-off-by: Jordan Niethe <jniethe5@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 9 |
1 files changed, 3 insertions, 6 deletions
@@ -2576,9 +2576,6 @@ static void phb4_lane_eq_change(struct phb4 *p, uint32_t vdid) p->lane_eq_en = !phb4_lane_eq_retry_whitelist(vdid); } -#define min(x,y) ((x) < (y) ? x : y) -#define max(x,y) ((x) < (y) ? x : y) - static bool phb4_link_optimal(struct pci_slot *slot, uint32_t *vdid) { struct phb4 *p = phb_to_phb4(slot->phb); @@ -2605,9 +2602,9 @@ static bool phb4_link_optimal(struct pci_slot *slot, uint32_t *vdid) phb4_get_info(slot->phb, bdfn, &dev_speed, &dev_width); /* Work out if we are optimally trained */ - target_speed = min(phb_speed, dev_speed); + target_speed = MIN(phb_speed, dev_speed); optimal_speed = (trained_speed >= target_speed); - target_width = min(phb_width, dev_width); + target_width = MIN(phb_width, dev_width); optimal_width = (trained_width >= target_width); optimal = optimal_width && optimal_speed; retry_enabled = (phb4_chip_retry_workaround() && @@ -3355,7 +3352,7 @@ static int64_t phb4_creset(struct pci_slot *slot) */ creset_time = tb_to_msecs(mftb() - p->creset_start_time); if (creset_time < 250) - wait_time = max(100, 250 - creset_time); + wait_time = MAX(100, 250 - creset_time); else wait_time = 100; PHBDBG(p, "CRESET: wait_time = %lld\n", wait_time); |