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| author | Nicholas Piggin <npiggin@gmail.com> | 2019-04-12 14:05:29 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2019-04-17 15:56:34 +1000 |
| commit | 53ef0db6e2efbf9678699db4a57df26cdd89e462 (patch) | |
| tree | 926c52210c2b53aeb73e910b7c0cb145e7d15ab0 | |
| parent | ac226d2c98ad95db44e1f2c27775c1b557af876b (diff) | |
| download | skiboot-53ef0db6e2efbf9678699db4a57df26cdd89e462.zip skiboot-53ef0db6e2efbf9678699db4a57df26cdd89e462.tar.gz skiboot-53ef0db6e2efbf9678699db4a57df26cdd89e462.tar.bz2 | |
asm/head.S: set POWER9 radix HID bit at entry
When running in virtual memory mode, the radix MMU hid bit should not
be changed, so set this in the initial boot SPR setup.
As a side effect, fast reboot also has HID0:RADIX bit set by the
shared spr init, so no need for an explicit call.
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
| -rw-r--r-- | asm/head.S | 3 | ||||
| -rw-r--r-- | core/cpu.c | 18 | ||||
| -rw-r--r-- | core/init.c | 3 | ||||
| -rw-r--r-- | include/cpu.h | 1 |
4 files changed, 5 insertions, 20 deletions
@@ -766,9 +766,12 @@ init_shared_sprs: mtspr SPR_TSCR, %r3 /* HID0: Clear bit 5 (enable core recovery) * Clear bit 4 (HILE) + * Set bit 8 (radix) */ mfspr %r3,SPR_HID0 li %r0,1 + sldi %r4,%r0,(63-8) + or %r3,%r3,%r4 sldi %r4,%r0,(63-5) sldi %r5,%r0,(63-4) or %r0,%r4,%r5 @@ -1433,20 +1433,6 @@ static int64_t cpu_change_all_hid0(struct hid0_change_req *req) return OPAL_SUCCESS; } -void cpu_set_radix_mode(void) -{ - struct hid0_change_req req; - - if (!radix_supported) - return; - - req.clr_bits = 0; - req.set_bits = SPR_HID0_POWER9_RADIX; - cleanup_global_tlb(); - current_radix_mode = true; - cpu_change_all_hid0(&req); -} - static void cpu_cleanup_one(void *param __unused) { mtspr(SPR_AMR, 0); @@ -1488,8 +1474,8 @@ void cpu_fast_reboot_complete(void) /* Fast reboot will have cleared HID0:HILE */ current_hile_mode = false; - /* On P9, restore radix mode */ - cpu_set_radix_mode(); + /* and set HID0:RADIX */ + current_radix_mode = true; } static int64_t opal_reinit_cpus(uint64_t flags) diff --git a/core/init.c b/core/init.c index eeee2d9..0fe6c16 100644 --- a/core/init.c +++ b/core/init.c @@ -1282,9 +1282,6 @@ void __noreturn __nomcount main_cpu_entry(const void *fdt) prd_register_reserved_memory(); - /* On P9, switch to radix mode by default */ - cpu_set_radix_mode(); - checksum_romem(); load_and_boot_kernel(false); diff --git a/include/cpu.h b/include/cpu.h index 39071a1..011b12b 100644 --- a/include/cpu.h +++ b/include/cpu.h @@ -313,7 +313,6 @@ extern unsigned long __attrconst cpu_emergency_stack_top(unsigned int pir); extern void cpu_idle_job(void); extern void cpu_idle_delay(unsigned long delay); -extern void cpu_set_radix_mode(void); extern void cpu_fast_reboot_complete(void); int dctl_set_special_wakeup(struct cpu_thread *t); |