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| author | Vaibhav Jain <vaibhav@linux.ibm.com> | 2018-08-23 15:37:49 +0530 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.ibm.com> | 2018-10-16 18:26:24 +1100 |
| commit | c8e1d61ae2c94d3ac5d4598800f793b313726b2a (patch) | |
| tree | 0b72e67ee72c963be624adc14677eff27d928d16 | |
| parent | d5ebd5519dcd1727bd2355d9e5aa4bfbcd7f3792 (diff) | |
| download | skiboot-c8e1d61ae2c94d3ac5d4598800f793b313726b2a.zip skiboot-c8e1d61ae2c94d3ac5d4598800f793b313726b2a.tar.gz skiboot-c8e1d61ae2c94d3ac5d4598800f793b313726b2a.tar.bz2 | |
phb4: Enable PHB MMIO-0/1 Bars only when mmio window exists
Presently phb4_probe_stack() will always enable PHB MMIO0/1 windows
even if they doesn't exist in phy_map. Hence we do some minor shuffling
in the phb4_probe_stack() so that MMIO-0/1 Bars are only enabled if
there corresponding MMIO window exists in the phy_map. In case phy_map
for an mmio window is '0' we set the corresponding BAR register to
'0'.
Signed-off-by: Vaibhav Jain <vaibhav@linux.ibm.com>
Reviewed-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
| -rw-r--r-- | hw/phb4.c | 3 |
1 files changed, 1 insertions, 2 deletions
@@ -5609,7 +5609,7 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, uint32_t pci_stack, nest_stack, etu_base, gcid, phb_num, stk_index; uint64_t val, phb_bar = 0, irq_bar = 0, bar_en; uint64_t mmio0_bar = 0, mmio0_bmask, mmio0_sz; - uint64_t mmio1_bar, mmio1_bmask, mmio1_sz; + uint64_t mmio1_bar = 0, mmio1_bmask, mmio1_sz; uint64_t reg[4]; void *foo; uint64_t mmio_win[4]; @@ -5668,7 +5668,6 @@ static void phb4_probe_stack(struct dt_node *stk_node, uint32_t pec_index, mmio1_bmask = (~(mmio1_sz - 1)) & 0x00FFFFFFFFFFFFFFULL; xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR1, mmio1_bar << 8); xscom_write(gcid, nest_stack + XPEC_NEST_STK_MMIO_BAR1_MASK, mmio1_bmask << 8); - bar_en |= XPEC_NEST_STK_BAR_EN_MMIO0 | XPEC_NEST_STK_BAR_EN_MMIO1; /* Build MMIO windows list */ mmio_win_sz = 0; |