lpc: Clear sync no-response field prior to device probe

Artem Senichev reported[1] his P8 platform was failing to boot from
a43e9a66aae9 ("astbmc: Fail SFC init if SIO is unavailable") with the
following error:

[  110.097168975,3] PLAT: Failed to open PNOR flash controller

I reproduced this behaviour on a Palmetto; we need to ensure the state
of the no-response error bit is clear before proceding with the presence
test.

The fix appears to resolve the failure to open the PNOR flash controller
on Palmetto and doesn't change the expected behaviour on Witherspoon.

[1] https://github.com/open-power/skiboot/issues/197

Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Tested-by: Artem Senichev <a.senichev@yadro.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>

1 files changed, 6 insertions, 1 deletions

diff --git a/hw/lpc.c b/hw/lpc.c
index c55d476..20e54c9 100644
--- a/hw/lpc.c
+++ b/hw/lpc.c
@@ -473,6 +473,7 @@ static const struct lpc_error_entry lpc_error_table[] = {
 static int64_t lpc_probe_prepare(struct lpcm *lpc)
 {
 	const uint32_t irqmask_addr = lpc_reg_opb_base + LPC_HC_IRQMASK;
+	const uint32_t irqstat_addr = lpc_reg_opb_base + LPC_HC_IRQSTAT;
 	uint32_t irqmask;
 	int rc;
 
@@ -481,7 +482,11 @@ static int64_t lpc_probe_prepare(struct lpcm *lpc)
 		return rc;
 
 	irqmask &= ~LPC_HC_IRQ_SYNC_NORESP_ERR;
-	return opb_write(lpc, irqmask_addr, irqmask, 4);
+	rc = opb_write(lpc, irqmask_addr, irqmask, 4);
+	if (rc)
+		return rc;
+
+	return opb_write(lpc, irqstat_addr, LPC_HC_IRQ_SYNC_NORESP_ERR, 4);
 }
 
 static int64_t lpc_probe_test(struct lpcm *lpc)