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| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-10-23 11:03:02 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-09 16:55:21 -0600 |
| commit | a05054c53a37850a2118d01fcf6669ebb10d1a33 (patch) | |
| tree | 531f018fadf6e8b6c12ca0a4d85cd5aa157ef0b4 | |
| parent | eb858339cae8240367c82e6c2cc139519dbddb26 (diff) | |
| download | skiboot-a05054c53a37850a2118d01fcf6669ebb10d1a33.zip skiboot-a05054c53a37850a2118d01fcf6669ebb10d1a33.tar.gz skiboot-a05054c53a37850a2118d01fcf6669ebb10d1a33.tar.bz2 | |
npu2: hw-procedures: Enable low power mode
Add a procedure which sets the NTL low power config register.
To actually enter low power mode, a corresponding change must be present
in the GPU device driver. The link will not enter low power mode unless
both sides agree, which means this change is safe to make independently.
It should have no forward or backward dependencies on other components.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2-hw-procedures.c | 19 | ||||
| -rw-r--r-- | include/npu2-regs.h | 6 |
2 files changed, 24 insertions, 1 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 7a5d188..85c2427 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -320,9 +320,26 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_RX_E_INTEG_COARSE_GAIN, lane, 11); } + return PROCEDURE_NEXT; +} + +/* Procedure 1.2.11 - Enable Low Power Mode */ +static uint32_t enable_low_power(struct npu2_dev *ndev) +{ + uint64_t val; + + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_ONLY_MODE, val, 1); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 22); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 68); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 68); + val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 477); + npu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val); + return PROCEDURE_COMPLETE; } -DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete); +DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete, + enable_low_power); /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */ static uint32_t phy_tx_zcal(struct npu2_dev *ndev) diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 759404c..307e93b 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -248,6 +248,12 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_NTL_MISC_CFG1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0C0) #define NPU2_NTL_SCRATCH1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0D0) #define NPU2_NTL_LOW_POWER_CFG(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0E0) +#define NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE PPC_BIT(0) +#define NPU2_NTL_LOW_POWER_CFG_ONLY_MODE PPC_BIT(1) +#define NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG PPC_BITMASK(2,7) +#define NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH PPC_BITMASK(8,19) +#define NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH PPC_BITMASK(20,31) +#define NPU2_NTL_LOW_POWER_CFG_CNT_THRESH PPC_BITMASK(32,43) #define NPU2_NTL_DBG_INHIBIT_CFG(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x220) #define NPU2_NTL_DISPLAY_CTL(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x280) #define NPU2_NTL_DISPLAY_DATA0(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x288) |