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authorMichael Neuling <mikey@neuling.org>2017-10-18 14:55:21 +1100
committerStewart Smith <stewart@linux.vnet.ibm.com>2017-10-18 19:22:53 -0500
commit62ac7631ae266e77ed16b2e8a43412c9a5207537 (patch)
treef49308bfd57848608dca5c4d48806b2ac2f5270f
parente2bc5cde8c77e63d62d79a09eaa4459aea906506 (diff)
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phb4: Fix PCIe GEN4 on DD2.1 and above
In this change: eef0e197ab PHB4: Default to PCIe GEN3 on POWER9 DD2.00 We clamped DD2.00 parts to GEN3 but unfortunately this change also applies to DD2.1 and above. This fixes this to only apply to DD2.00. This also cleans up the documentation and printing. Signed-off-by: Michael Neuling <mikey@neuling.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
-rw-r--r--hw/phb4.c7
1 files changed, 3 insertions, 4 deletions
diff --git a/hw/phb4.c b/hw/phb4.c
index 2b7c417..c64ded9 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -4895,14 +4895,13 @@ static void phb4_create(struct dt_node *np)
if (!phb4_read_capabilities(p))
goto failed;
- /* Priority order: NVRAM -> dt -> GEN2 dd1 -> GEN4 */
+ /* Priority order: NVRAM -> dt -> GEN2 dd1 -> GEN3 dd2.00 -> GEN4 */
p->max_link_speed = 4;
if (p->rev == PHB4_REV_NIMBUS_DD10)
p->max_link_speed = 2;
- if (p->rev == PHB4_REV_NIMBUS_DD20 && chip->ec_rev == 0) {
+ if (p->rev == PHB4_REV_NIMBUS_DD20 &&
+ chip->ec_level == 0 && chip->ec_rev == 0)
p->max_link_speed = 3;
- PHBINF(p, "Default max link speed for P9 DD2.00 is GEN3\n");
- }
if (dt_has_node_property(np, "ibm,max-link-speed", NULL))
p->max_link_speed = dt_prop_get_u32(np, "ibm,max-link-speed");
if (pcie_max_link_speed)