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| author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2019-05-29 16:58:59 +1000 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2020-03-27 16:35:47 +0530 |
| commit | 5d0f9c6ace746dc4f006e090665bb536c74022cb (patch) | |
| tree | 0fa58a35e56b99ed8462fadb0c8f1f6f2c3e7b76 | |
| parent | 5bea4174fda5a43f7ccaa966ba9487a4322df3ec (diff) | |
| download | skiboot-5d0f9c6ace746dc4f006e090665bb536c74022cb.zip skiboot-5d0f9c6ace746dc4f006e090665bb536c74022cb.tar.gz skiboot-5d0f9c6ace746dc4f006e090665bb536c74022cb.tar.bz2 | |
npu2: Clear fence state for a brick being reset
[ Upstream commit d496bb141c978a6dc8a106b3d92e5fc1ad0f8663 ]
Resetting a GPU before resetting an NVLink leads to occasional HMIs
which fence some bricks and prevent the "reset_ntl" procedure from
succeeding at the "reset_ntl_release" step - the host system requires
reboot; there may be other cases like this as well.
This adds clearing of the fence bit in NPU.MISC.FENCE_STATE for
the NVLink which we are about to reset.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2-hw-procedures.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 2a03bed..6c8dee9 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -256,6 +256,14 @@ uint32_t reset_ntl(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_TX_LANE_PDWN, lane, 0); } + /* Clear fence state for the brick */ + val = npu2_read(ndev->npu, NPU2_MISC_FENCE_STATE); + if (val & PPC_BIT(ndev->brick_index)) { + NPU2DEVINF(ndev, "Clearing brick fence\n"); + val = PPC_BIT(ndev->brick_index); + npu2_write(ndev->npu, NPU2_MISC_FENCE_STATE, val); + } + /* Write PRI */ val = SETFIELD(PPC_BITMASK(0,1), 0ull, obus_brick_index(ndev)); npu2_write_mask(ndev->npu, NPU2_NTL_PRI_CFG(ndev), val, -1ULL); |