phb4: Disable 32-bit MSI in capi mode

If a capi device does a DMA write targeting an address lower than 4GB,
it does so through a 32-bit operation, per the PCI spec. In capi mode,
the first TVE entry is configured in bypass mode, so the address is
valid. But with any (bad) luck, the address could be 0xFFFFxxxx, thus
looking like a 32-bit MSI.

We currently enable both 32-bit and 64-bit MSIs, so the PHB will
interpret the DMA write as a MSI, which very likely results in an EEH
(MSI with a bad payload size).

We can fix it by disabling 32-bit MSI when switching the PHB to capi
mode. Capi devices are 64-bit.

Cc: stable
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
(cherry picked from commit 3b9bc869a4fee22c99a4d24ba87ce938d46b11f4)
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>

1 files changed, 9 insertions, 0 deletions

diff --git a/hw/phb4.c b/hw/phb4.c
index 61ee54a..43a3110 100644
--- a/hw/phb4.c
+++ b/hw/phb4.c
@@ -4108,6 +4108,15 @@ static int64_t enable_capi_mode(struct phb4 *p, uint64_t pe_number,
 	for (i = 0; i < p->tvt_size; i++)
 		out_be64(p->regs + PHB_IODA_DATA0, p->tve_cache[i]);
 
+	/*
+	 * Since TVT#0 is in by-pass mode, disable 32-bit MSI, as a
+	 * DMA write targeting 0x00000000FFFFxxxx would be interpreted
+	 * as a 32-bit MSI
+	 */
+	reg = in_be64(p->regs + PHB_PHB4_CONFIG);
+	reg &= ~PHB_PHB4C_32BIT_MSI_EN;
+	out_be64(p->regs + PHB_PHB4_CONFIG, reg);
+
 	/* set mbt bar to pass capi mmio window and keep the other
 	 * mmio values
 	 */