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| author | Michael Neuling <mikey@neuling.org> | 2017-11-14 22:23:02 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-15 02:29:38 -0600 |
| commit | 0a3df98b0a7ed3c4b61755fd26ab48c804a7c041 (patch) | |
| tree | 9ba332a3336f2b9808344a9657a8cb5708f909de | |
| parent | 0cc1fe4e23308fc4f4002c74b475475e96fedcb9 (diff) | |
| download | skiboot-0a3df98b0a7ed3c4b61755fd26ab48c804a7c041.zip skiboot-0a3df98b0a7ed3c4b61755fd26ab48c804a7c041.tar.gz skiboot-0a3df98b0a7ed3c4b61755fd26ab48c804a7c041.tar.bz2 | |
npu2: Create npu2_write_mcd()
This code is replicated, so let's put it in a function. Also add some cleanups.
No functional change.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
(cherry picked from commit 4f4bf83128c1d944782f02b238e632ed8d2451af)
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2.c | 24 | ||||
| -rw-r--r-- | include/npu2-regs.h | 3 |
2 files changed, 19 insertions, 8 deletions
@@ -845,6 +845,20 @@ static int64_t npu2_ioda_reset(struct phb *phb, bool purge) return OPAL_SUCCESS; } +static void npu2_write_mcd(struct npu2 *p, uint64_t pcb_addr, uint64_t addr, + uint64_t size) +{ + uint64_t val; + + NPU2DBG(p, "Setting MCD addr:%llx\n", pcb_addr); + assert(is_pow2(size)); + + val = MCD_BANK_CN_VALID; + val = SETFIELD(MCD_BANK_CN_SIZE, val, (size >> 25) - 1); + val = SETFIELD(MCD_BANK_CN_ADDR, val, addr >> 25); + xscom_write(p->chip_id, pcb_addr, val); +} + static void npu2_hw_init(struct npu2 *p) { int i; @@ -884,10 +898,7 @@ static void npu2_hw_init(struct npu2 *p) /* Allocate the biggest chunk first as we assume gpu_max_addr has the * highest alignment. */ addr = gpu_max_addr - size; - val = PPC_BIT(0); - val = SETFIELD(PPC_BITMASK(13, 29), val, (size >> 25) - 1); - val = SETFIELD(PPC_BITMASK(33, 63), val, addr >> 25); - xscom_write(p->chip_id, MCD0_BANK0_CN3, val); + npu2_write_mcd(p, MCD0_BANK0_CN3, addr, size); total_size -= size; if (total_size) { /* total_size was not a power of two, but the remainder should @@ -896,10 +907,7 @@ static void npu2_hw_init(struct npu2 *p) size = 1ull << ilog2(total_size); addr -= size; assert(addr <= gpu_min_addr); - val = PPC_BIT(0); - val = SETFIELD(PPC_BITMASK(13, 29), val, (size >> 25) - 1); - val = SETFIELD(PPC_BITMASK(33, 63), val, addr >> 25); - xscom_write(p->chip_id, MCD1_BANK0_CN3, val); + npu2_write_mcd(p, MCD1_BANK0_CN3, addr, size); } } diff --git a/include/npu2-regs.h b/include/npu2-regs.h index d35cc44..55af252 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -28,6 +28,9 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); * code */ #define MCD0_BANK0_CN3 0x301100d #define MCD1_BANK0_CN3 0x301140d +#define MCD_BANK_CN_VALID PPC_BIT(0) +#define MCD_BANK_CN_SIZE PPC_BITMASK(13,29) +#define MCD_BANK_CN_ADDR PPC_BITMASK(33,63) #define NPU2_REG_OFFSET(stack, block, offset) \ (((stack) << 20) | ((block) << 16) | (offset)) |