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| author | Reza Arbab <arbab@linux.vnet.ibm.com> | 2017-11-27 18:10:53 -0600 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-28 15:29:46 -0600 |
| commit | f52024f3aae7f094fa9ceab2deff572e9b63e7b0 (patch) | |
| tree | 8eb1840bd749dc9fa533bd8ba07badf143ecd337 | |
| parent | 36402ae1e429d47cc73124eb7b03495ef9a7129b (diff) | |
| download | skiboot-f52024f3aae7f094fa9ceab2deff572e9b63e7b0.zip skiboot-f52024f3aae7f094fa9ceab2deff572e9b63e7b0.tar.gz skiboot-f52024f3aae7f094fa9ceab2deff572e9b63e7b0.tar.bz2 | |
npu2: hw-procedures: Manipulate IOVALID during training
Ensure that the IOVALID bit for this brick is raised at the start of
link training, in the reset_ntl procedure.
Then, to protect us from a glitch when the PHY clock turns off or gets
chopped, lower IOVALID for the duration of the phy_reset and
phy_rx_dccal procedures.
Signed-off-by: Reza Arbab <arbab@linux.vnet.ibm.com>
Acked-By: Alistair Popple <alistair@popple.id.au>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
(cherry picked from commit 4e04c833a1d460d706d9c4fec16a951d75a52efb)
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2-hw-procedures.c | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 4c9d843..879ffe7 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -203,6 +203,20 @@ static int obus_brick_index(struct npu2_dev *ndev) return index; } +static void set_iovalid(struct npu2_dev *ndev, bool raise) +{ + uint64_t addr, val, mask; + int rc; + + addr = (ndev->pl_xscom_base & 0x3F000000) | 0x9; + mask = PPC_BIT(6 + obus_brick_index(ndev)); + val = raise ? mask : 0; + + rc = xscom_write_mask(ndev->npu->chip_id, addr, val, mask); + if (rc) + NPU2DEVERR(ndev, "error %d writing scom 0x%llx\n", rc, addr); +} + static bool poll_fence_status(struct npu2_dev *ndev, uint64_t val) { uint64_t fs; @@ -223,6 +237,8 @@ static uint32_t reset_ntl(struct npu2_dev *ndev) { uint64_t val; + set_iovalid(ndev, true); + /* Write PRI */ val = SETFIELD(PPC_BITMASK(0,1), 0ull, obus_brick_index(ndev)); npu2_write_mask(ndev->npu, NPU2_NTL_PRI_CFG(ndev), val, -1ULL); @@ -304,6 +320,8 @@ static uint32_t phy_reset(struct npu2_dev *ndev) { int lane; + set_iovalid(ndev, false); + /* Power on clocks */ phy_write(ndev, &NPU2_PHY_RX_CLKDIST_PDWN, 0); phy_write(ndev, &NPU2_PHY_RX_IREF_PDWN, 1); @@ -360,6 +378,8 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_RX_E_INTEG_COARSE_GAIN, lane, 11); } + set_iovalid(ndev, true); + return PROCEDURE_COMPLETE; } DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete); @@ -572,6 +592,8 @@ static uint32_t phy_rx_dccal(struct npu2_dev *ndev) { int lane; + set_iovalid(ndev, false); + FOR_EACH_LANE(ndev, lane) phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 1); @@ -598,6 +620,8 @@ static uint32_t phy_rx_dccal_complete(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_RX_PR_FW_OFF, lane, 0); } + set_iovalid(ndev, true); + return PROCEDURE_NEXT; } |