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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-11-16 11:36:06 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-15 21:11:15 -0600 |
| commit | bb58eed0de1f310830361b0b54be1df125e66b8d (patch) | |
| tree | 2e63f837ee9e98bfc1356b8a80539a4f8ac54c54 | |
| parent | 31f90050849283261e300619e63f9bb0deb5862d (diff) | |
| download | skiboot-bb58eed0de1f310830361b0b54be1df125e66b8d.zip skiboot-bb58eed0de1f310830361b0b54be1df125e66b8d.tar.gz skiboot-bb58eed0de1f310830361b0b54be1df125e66b8d.tar.bz2 | |
phb4: Fix PE mapping of M32 BAR
The M32 BAR is the PHB4 region used to map all the non-prefetchable
or 32-bit device BARs. It's supposed to have its segments remapped
via the MDT and Linux relies on that to assign them individual PE#.
However, we weren't configuring that properly and instead used the
mode where PE# == segment#, thus causing EEH to freeze the wrong
device or PE#.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
(cherry picked from commit 4002ea166fde4b4e44f6571027c60c6b75df5c33)
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 24 |
1 files changed, 11 insertions, 13 deletions
@@ -873,19 +873,15 @@ static uint64_t phb4_default_mbt0(struct phb4 *p, unsigned int bar_idx) switch (p->mbt_size - bar_idx - 1) { case 0: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); - mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 0); + mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 3); break; case 1: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); - mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 1); - break; - case 2: - mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 2); break; - case 3: + case 2: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); - mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 3); + mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 1); break; default: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_PE_SEG); @@ -957,16 +953,18 @@ static void phb4_init_ioda_cache(struct phb4 *p) } } - for (i = 0; i < p->mbt_size; i++) { + + /* Initialize MBT entries for BARs 1...N */ + for (i = 1; i < p->mbt_size; i++) { p->mbt_cache[i][0] = phb4_default_mbt0(p, i); p->mbt_cache[i][1] = 0; } - /* Initialise M32 bar using MDT entry 0 */ - p->mbt_cache[0][0] |= IODA3_MBT0_TYPE_M32 | - (p->mm1_base & IODA3_MBT0_BASE_ADDR); - p->mbt_cache[0][1] = IODA3_MBT1_ENABLE | - ((~(M32_PCI_SIZE - 1)) & IODA3_MBT1_MASK); + /* Initialize M32 bar using MBT entry 0, MDT colunm A */ + p->mbt_cache[0][0] = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); + p->mbt_cache[0][0] |= SETFIELD(IODA3_MBT0_MDT_COLUMN, 0ull, 0); + p->mbt_cache[0][0] |= IODA3_MBT0_TYPE_M32 | (p->mm1_base & IODA3_MBT0_BASE_ADDR); + p->mbt_cache[0][1] = IODA3_MBT1_ENABLE | ((~(M32_PCI_SIZE - 1)) & IODA3_MBT1_MASK); } static int64_t phb4_wait_bit(struct phb4 *p, uint32_t reg, |