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| author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-06-24 14:17:08 -0500 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-06-26 14:28:58 +1000 |
| commit | ead3cafd000b003ddda4c27989e30d239a91d8be (patch) | |
| tree | 069c88eb8f8a6f174738f1ac216b27688e522487 | |
| parent | 2c7699552327978f89ae606185e99ad8ebdfdcd1 (diff) | |
| download | skiboot-ead3cafd000b003ddda4c27989e30d239a91d8be.zip skiboot-ead3cafd000b003ddda4c27989e30d239a91d8be.tar.gz skiboot-ead3cafd000b003ddda4c27989e30d239a91d8be.tar.bz2 | |
phb4: Workaround bug in spec 053
Wait for DLP PGRESET to clear *after* lifting the PCIe core reset
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 7 |
1 files changed, 5 insertions, 2 deletions
@@ -3544,8 +3544,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init) in_be64(p->regs + PHB_PCIE_SCR)); /* Init_5 - Wait for DLP PGRESET to clear */ - if (!phb4_wait_dlp_reset(p)) - goto failed; + /* This is broken in spec 053, moving that step to after Init_16 */ /* Init_6 - deassert CFG reset */ creset = in_be64(p->regs + PHB_PCIE_CRESET); @@ -3582,6 +3581,10 @@ static void phb4_init_hw(struct phb4 *p, bool first_init) creset |= PHB_PCIE_CRESET_PIPE_N; out_be64(p->regs + PHB_PCIE_CRESET, creset); + /* (Moved from Init_5) */ + if (!phb4_wait_dlp_reset(p)) + goto failed; + /* Init_17 - PHB Control */ val = PHB_CTRLR_IRQ_PGSZ_64K; if (p->rev == PHB4_REV_NIMBUS_DD10) { |