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| author | Michael Neuling <mikey@neuling.org> | 2017-11-14 22:23:04 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-11-15 02:29:38 -0600 |
| commit | 6dd34d9592a27116b68175eebf6b0f0891f8bb02 (patch) | |
| tree | 5af521375e0a5dddf8f56510dbcc74c28f27a40d | |
| parent | 2dbbcddb43b7f14b879c5ab45d9d6abef8763922 (diff) | |
| download | skiboot-6dd34d9592a27116b68175eebf6b0f0891f8bb02.zip skiboot-6dd34d9592a27116b68175eebf6b0f0891f8bb02.tar.gz skiboot-6dd34d9592a27116b68175eebf6b0f0891f8bb02.tar.bz2 | |
npu2: MCD refactor
Pull out MCD writing code into npu2_mcd_init()
No functional change.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Acked-by: Balbir Singh <bsingharora@gmail.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
(cherry picked from commit 75371796ac595a4ce2f1b6bd254f5f3ad7416a96)
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/npu2.c | 33 |
1 files changed, 20 insertions, 13 deletions
@@ -860,21 +860,10 @@ static void npu2_write_mcd(struct npu2 *p, uint64_t pcb_addr, uint64_t addr, xscom_write(p->chip_id, pcb_addr, val); } -static void npu2_hw_init(struct npu2 *p) +static void npu2_mcd_init(struct npu2 *p) { int i; - uint64_t val, size, addr, gpu_min_addr, gpu_max_addr, total_size; - - npu2_ioda_reset(&p->phb, false); - - /* Enable XTS retry mode */ - val = npu2_read(p, NPU2_XTS_CFG); - npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); - - if (!is_p9dd1()) { - val = npu2_read(p, NPU2_XTS_CFG2); - npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); - } + uint64_t size, addr, gpu_min_addr, gpu_max_addr, total_size; /* Init memory cache directory (MCD) registers. */ phys_map_get(p->chip_id, GPU_MEM, NPU2_LINKS_PER_CHIP - 1, @@ -912,6 +901,24 @@ static void npu2_hw_init(struct npu2 *p) } } +static void npu2_hw_init(struct npu2 *p) +{ + uint64_t val; + + npu2_ioda_reset(&p->phb, false); + + /* Enable XTS retry mode */ + val = npu2_read(p, NPU2_XTS_CFG); + npu2_write(p, NPU2_XTS_CFG, val | NPU2_XTS_CFG_MMIOSD | NPU2_XTS_CFG_TRY_ATR_RO); + + if (!is_p9dd1()) { + val = npu2_read(p, NPU2_XTS_CFG2); + npu2_write(p, NPU2_XTS_CFG2, val | NPU2_XTS_CFG2_NO_FLUSH_ENA); + } + + npu2_mcd_init(p); +} + static int64_t npu2_map_pe_dma_window_real(struct phb *phb, uint64_t pe_num, uint16_t window_id, |