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| author | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-18 14:21:57 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-09-19 04:13:00 -0500 |
| commit | eef0e197abbdc0ce8034be94cd7022e498f11c3e (patch) | |
| tree | c651daedaa17680c8db6df96ac7310a27fe847f2 | |
| parent | 6dd6a710a7ebcf6bdf81c5b49ed64d819d779987 (diff) | |
| download | skiboot-eef0e197abbdc0ce8034be94cd7022e498f11c3e.zip skiboot-eef0e197abbdc0ce8034be94cd7022e498f11c3e.tar.gz skiboot-eef0e197abbdc0ce8034be94cd7022e498f11c3e.tar.bz2 | |
PHB4: Default to PCIe GEN3 on POWER9 DD2.00
You can use the NVRAM override for DD2.00 screened parts.
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -4741,12 +4741,14 @@ static void phb4_create(struct dt_node *np) char *path; uint32_t irq_base, irq_flags; int i; + struct proc_chip *chip; assert(p); /* Populate base stuff */ p->index = dt_prop_get_u32(np, "ibm,phb-index"); p->chip_id = dt_prop_get_u32(np, "ibm,chip-id"); + chip = get_chip(p->chip_id); p->regs = (void *)dt_get_address(np, 0, NULL); p->int_mmio = (void *)dt_get_address(np, 1, NULL); p->phb.dt_node = np; @@ -4833,6 +4835,10 @@ static void phb4_create(struct dt_node *np) p->max_link_speed = 4; if (p->rev == PHB4_REV_NIMBUS_DD10) p->max_link_speed = 2; + if (p->rev == PHB4_REV_NIMBUS_DD20 && chip->ec_rev == 0) { + p->max_link_speed = 3; + PHBINF(p, "Default max link speed for P9 DD2.00 is GEN3\n"); + } if (dt_has_node_property(np, "ibm,max-link-speed", NULL)) p->max_link_speed = dt_prop_get_u32(np, "ibm,max-link-speed"); if (pcie_max_link_speed) |