diff options
| author | Michael Neuling <mikey@neuling.org> | 2017-07-12 12:06:49 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-07-13 10:19:45 +1000 |
| commit | e4da615a48ee94db1b73bf66fc1d7f94237d8bbb (patch) | |
| tree | ee8123dcce63e81c6ea4c49592d3b2b0b26156e2 | |
| parent | 95f8a8c36a90c31ae9006e8e17d7c26a6b7eb7c9 (diff) | |
| download | skiboot-e4da615a48ee94db1b73bf66fc1d7f94237d8bbb.zip skiboot-e4da615a48ee94db1b73bf66fc1d7f94237d8bbb.tar.gz skiboot-e4da615a48ee94db1b73bf66fc1d7f94237d8bbb.tar.bz2 | |
phb4: Only set one bit in nfir
The MPIPL procedure says to only set bit 26 when forcing the PEC into
freeze mode. Currently we set bits 24-27.
This changes the code to follow spec and only set bit 26.
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 2 |
1 files changed, 1 insertions, 1 deletions
@@ -2405,7 +2405,7 @@ static int64_t phb4_creset(struct pci_slot *slot) /* Force fence on the PHB to work around a non-existent PE */ if (!phb4_fenced(p)) xscom_write(p->chip_id, p->pe_stk_xscom + 0x2, - 0x000000f000000000); + 0x0000002000000000); /* * Force use of ASB for register access until the PHB has |