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| author | Frederic Barrat <fbarrat@linux.vnet.ibm.com> | 2018-01-23 20:57:11 +0100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2018-01-30 20:42:38 -0600 |
| commit | 4f24ef23411d270ef392e1dc280479c0f5304305 (patch) | |
| tree | 6d3645b97a4ab5a24808a521360913df15c9f8ac | |
| parent | ea9b3080559a995ef80772749b36da3031b388a4 (diff) | |
| download | skiboot-4f24ef23411d270ef392e1dc280479c0f5304305.zip skiboot-4f24ef23411d270ef392e1dc280479c0f5304305.tar.gz skiboot-4f24ef23411d270ef392e1dc280479c0f5304305.tar.bz2 | |
xive: Mask MMIO load/store to bad location FIR
For opencapi, the trigger page of an interrupt is mapped to user
space. The intent is to write the page to raise an interrupt but
there's nothing to prevent a user process from reading it, which has
the infortunate consequence of checkstopping the system.
Mask the FIR bit raised when an MMIO operation targets an invalid
location. It's the recommendation from recent documentation and
hostboot is expected to mask it at some point. In the meantime, let's
play it safe.
Signed-off-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/xive.c | 8 | ||||
| -rw-r--r-- | include/xive.h | 2 |
2 files changed, 9 insertions, 1 deletions
@@ -1774,7 +1774,13 @@ static bool xive_config_init(struct xive *x) /* Disable error reporting in the FIR for info errors * from the VC. */ - xive_regw(x, CQ_FIRMASK_OR, 3ull); + xive_regw(x, CQ_FIRMASK_OR, CQ_FIR_VC_INFO_ERROR_0_1); + + /* Mask CI Load and Store to bad location, as IPI trigger + * pages may be mapped to user space, and a read on the + * trigger page causes a checkstop + */ + xive_regw(x, CQ_FIRMASK_OR, CQ_FIR_PB_RCMDX_CI_ERR1); return true; } diff --git a/include/xive.h b/include/xive.h index 5262cb4..47dc2c2 100644 --- a/include/xive.h +++ b/include/xive.h @@ -72,6 +72,8 @@ #define CQ_RST_CTL 0x118 #define X_CQ_FIRMASK 0x33 #define CQ_FIRMASK 0x198 +#define CQ_FIR_PB_RCMDX_CI_ERR1 PPC_BIT(19) +#define CQ_FIR_VC_INFO_ERROR_0_1 PPC_BITMASK(62,63) #define X_CQ_FIRMASK_AND 0x34 #define CQ_FIRMASK_AND 0x1a0 #define X_CQ_FIRMASK_OR 0x35 |