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| author | Russell Currey <ruscur@russell.cc> | 2017-08-10 16:58:42 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-11 16:37:24 +1000 |
| commit | e29d8492499600118807ce1fde17acbd4e0cb7b9 (patch) | |
| tree | 3541d7be81cf127437ef758be845c6f892e5757a | |
| parent | 500bda26c564b218a9ae392c6d8b20bb952e4595 (diff) | |
| download | skiboot-e29d8492499600118807ce1fde17acbd4e0cb7b9.zip skiboot-e29d8492499600118807ce1fde17acbd4e0cb7b9.tar.gz skiboot-e29d8492499600118807ce1fde17acbd4e0cb7b9.tar.bz2 | |
phb4: Ignore slot state if performing complete reset
If a PHB is being completely reset, its state is about to be blown away
anyway, so if it's not in an appropriate state, creset it regardless.
Signed-off-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 5 |
1 files changed, 4 insertions, 1 deletions
@@ -2700,8 +2700,11 @@ static int64_t phb4_creset(struct pci_slot *slot) pci_slot_set_state(slot, PHB4_SLOT_NORMAL); return slot->ops.freset(slot); default: - PHBERR(p, "CRESET: Unexpected slot state %08x\n", + PHBERR(p, "CRESET: Unexpected slot state %08x, resetting...\n", slot->state); + pci_slot_set_state(slot, PHB4_SLOT_NORMAL); + return slot->ops.creset(slot); + } error: |