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| author | Michael Neuling <mikey@neuling.org> | 2017-07-26 20:50:02 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-07-28 14:03:59 +1000 |
| commit | a992835a27a08a7cd6722931201907a76398da09 (patch) | |
| tree | fecfc1ddac436ac99b453ac5decf9956b6db9393 | |
| parent | 860ef65c9781e29c1f887b70d15a6d25766b7832 (diff) | |
| download | skiboot-a992835a27a08a7cd6722931201907a76398da09.zip skiboot-a992835a27a08a7cd6722931201907a76398da09.tar.gz skiboot-a992835a27a08a7cd6722931201907a76398da09.tar.bz2 | |
phb4: Dump devctl and devstat registers
Dump devctl and devstat registers. These would have been useful when
debugging the MPS issue.
Suggested-by: Mike Perez <perezma@us.ibm.com>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 8 |
1 files changed, 8 insertions, 0 deletions
@@ -1888,6 +1888,7 @@ static void phb4_read_phb_status(struct phb4 *p, static void phb4_eeh_dump_regs(struct phb4 *p) { struct OpalIoPhb4ErrorData *s; + uint32_t reg; unsigned int i; s = zalloc(sizeof(struct OpalIoPhb4ErrorData)); @@ -1907,6 +1908,13 @@ static void phb4_eeh_dump_regs(struct phb4 *p) PHBERR(p, " corrErrorStatus = %08x\n", s->corrErrorStatus); PHBERR(p, " uncorrErrorStatus = %08x\n", s->uncorrErrorStatus); + /* Two non OPAL API registers that are useful */ + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVCTL, ®); + PHBERR(p, " devctl = %08x\n", reg); + phb4_pcicfg_read32(&p->phb, 0, p->ecap + PCICAP_EXP_DEVSTAT, + ®); + PHBERR(p, " devStat = %08x\n", reg); + /* Byte swap TLP headers so they are the same as the PCIe spec */ PHBERR(p, " tlpHdr1 = %08x\n", bswap_32(s->tlpHdr1)); PHBERR(p, " tlpHdr2 = %08x\n", bswap_32(s->tlpHdr2)); |