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author | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2017-03-15 20:58:59 +1100 |
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committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-03-16 17:18:01 +1100 |
commit | 523dbbcd6301f3bcbfb60d74a22b7482398b10f1 (patch) | |
tree | ede013e7870b26c5246b5794dd42e3ac4ead79ea | |
parent | d801ff7ff17faa94cb02b10d532130c57db8f70c (diff) | |
download | skiboot-523dbbcd6301f3bcbfb60d74a22b7482398b10f1.zip skiboot-523dbbcd6301f3bcbfb60d74a22b7482398b10f1.tar.gz skiboot-523dbbcd6301f3bcbfb60d74a22b7482398b10f1.tar.bz2 |
xive: Move xive_provision_cpu() around
More logical organisation of the code.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
-rw-r--r-- | hw/xive.c | 70 |
1 files changed, 35 insertions, 35 deletions
@@ -2848,41 +2848,6 @@ static void xive_setup_hw_for_emu(struct xive_cpu_state *xs) 0, 8, &vp, false, true); } -static void xive_provision_cpu(struct xive_cpu_state *xs, struct cpu_thread *c) -{ - struct xive *x; - void *p; - - /* Physical VPs are pre-allocated */ - xs->vp_blk = PIR2VP_BLK(c->pir); - xs->vp_idx = PIR2VP_IDX(c->pir); - - /* For now we use identical block IDs for VC and PC but that might - * change. We allocate the EQs on the same XIVE as the VP. - */ - xs->eq_blk = xs->vp_blk; - - /* Grab the XIVE where the EQ resides. It could be different from - * the local chip XIVE if not using block group mode - */ - x = xive_from_vc_blk(xs->eq_blk); - assert(x); - - /* Allocate a set of EQs for that VP */ - xs->eq_idx = xive_alloc_eq_set(x, true); - assert(!XIVE_ALLOC_IS_ERR(xs->eq_idx)); - - /* Provision one of the queues. Allocate the memory on the - * chip where the CPU resides - */ - p = local_alloc(c->chip_id, 0x10000, 0x10000); - if (!p) { - xive_err(x, "Failed to allocate EQ backing store\n"); - assert(false); - } - xs->eq_page = p; -} - static void xive_init_cpu_emulation(struct xive_cpu_state *xs, struct cpu_thread *cpu) { @@ -2955,6 +2920,41 @@ static void xive_configure_ex_special_bar(struct xive *x, struct cpu_thread *c) } } +static void xive_provision_cpu(struct xive_cpu_state *xs, struct cpu_thread *c) +{ + struct xive *x; + void *p; + + /* Physical VPs are pre-allocated */ + xs->vp_blk = PIR2VP_BLK(c->pir); + xs->vp_idx = PIR2VP_IDX(c->pir); + + /* For now we use identical block IDs for VC and PC but that might + * change. We allocate the EQs on the same XIVE as the VP. + */ + xs->eq_blk = xs->vp_blk; + + /* Grab the XIVE where the EQ resides. It could be different from + * the local chip XIVE if not using block group mode + */ + x = xive_from_vc_blk(xs->eq_blk); + assert(x); + + /* Allocate a set of EQs for that VP */ + xs->eq_idx = xive_alloc_eq_set(x, true); + assert(!XIVE_ALLOC_IS_ERR(xs->eq_idx)); + + /* Provision one of the queues. Allocate the memory on the + * chip where the CPU resides + */ + p = local_alloc(c->chip_id, 0x10000, 0x10000); + if (!p) { + xive_err(x, "Failed to allocate EQ backing store\n"); + assert(false); + } + xs->eq_page = p; +} + static void xive_init_cpu(struct cpu_thread *c) { struct proc_chip *chip = get_chip(c->chip_id); |