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| author | Philippe Bergheaud <felix@linux.vnet.ibm.com> | 2016-04-01 14:28:01 +0200 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-04-27 15:06:11 +1000 |
| commit | 21115731f292f6b9ee8a0967696306334d825fa9 (patch) | |
| tree | 5f274e51eeeb98074ce5179202ed55a3fabd21d2 | |
| parent | a51a84043aa9802cca1397c5a9276aea69b0af68 (diff) | |
| download | skiboot-21115731f292f6b9ee8a0967696306334d825fa9.zip skiboot-21115731f292f6b9ee8a0967696306334d825fa9.tar.gz skiboot-21115731f292f6b9ee8a0967696306334d825fa9.tar.bz2 | |
phb3: Test CAPI mode on both CAPP units on Naples
Naples has two capp units. The address of the PE Secure CAPP Enable
register for capp unit 1 is equal to the address for capp unit 0 + 0x40.
This patch introduces and uses the macro PE_REG_OFFSET, that returns
0x40 for the capp unit 1 on Naples, and 0x0 otherwise.
Signed-off-by: Philippe Bergheaud <felix@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb3.c | 7 |
1 files changed, 6 insertions, 1 deletions
@@ -3405,6 +3405,11 @@ static void phb3_init_capp_errors(struct phb3 *p) out_be64(p->regs + PHB_INB_ERR_AIB_FENCE_ENABLE, 0xfcffe0fbff7ff0ec); } +#define PE_CAPP_EN 0x9013c03 + +#define PE_REG_OFFSET(p) \ + ((PHB3_IS_NAPLES(p) && (p)->index) ? 0x40 : 0x0) + static int64_t phb3_set_capi_mode(struct phb *phb, uint64_t mode, uint64_t pe_number) { @@ -3472,7 +3477,7 @@ static int64_t phb3_set_capi_mode(struct phb *phb, uint64_t mode, if (mode != OPAL_PHB_CAPI_MODE_CAPI) return OPAL_UNSUPPORTED; - xscom_read(p->chip_id, 0x9013c03, ®); + xscom_read(p->chip_id, PE_CAPP_EN + PE_REG_OFFSET(p), ®); if (reg & PPC_BIT(0)) { PHBDBG(p, "Already in CAPP mode\n"); } |