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| author | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2019-07-12 16:47:53 +0530 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-15 17:53:49 +1000 |
| commit | fbd875d77f30ee9a713625c3f4400cde06e70ac8 (patch) | |
| tree | 3ebda0617472380f1e82bf6632ac104405545ddc | |
| parent | 0a17e674616413b7a3182643cfa0fda292141bb1 (diff) | |
| download | skiboot-fbd875d77f30ee9a713625c3f4400cde06e70ac8.zip skiboot-fbd875d77f30ee9a713625c3f4400cde06e70ac8.tar.gz skiboot-fbd875d77f30ee9a713625c3f4400cde06e70ac8.tar.bz2 | |
MPIPL: Save crashing PIR
Crashing CPU PIR is required to get proper backtrace from core file.
Save crashing CPU PIR before triggering MPIPL. Post MPIPL OPAL will
pass saved PIR to kernel and kernel will use that to create OPAL dump.
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
[oliver: rebased]
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
| -rw-r--r-- | core/opal-dump.c | 7 | ||||
| -rw-r--r-- | hw/sbe-p9.c | 4 | ||||
| -rw-r--r-- | include/opal-dump.h | 3 |
3 files changed, 14 insertions, 0 deletions
diff --git a/core/opal-dump.c b/core/opal-dump.c index 9ca01e5..bb90c45 100644 --- a/core/opal-dump.c +++ b/core/opal-dump.c @@ -16,6 +16,7 @@ #define pr_fmt(fmt) "DUMP: " fmt +#include <cpu.h> #include <device.h> #include <mem-map.h> #include <mem_region.h> @@ -328,6 +329,12 @@ static int64_t opal_mpipl_register_tag(enum opal_mpipl_tags tag, return rc; } +void opal_mpipl_save_crashing_pir(void) +{ + mpipl_metadata->crashing_pir = this_cpu()->pir; + prlog(PR_NOTICE, "Crashing PIR = 0x%x\n", this_cpu()->pir); +} + void opal_mpipl_init(void) { void *mdst_base = (void *)MDST_TABLE_BASE; diff --git a/hw/sbe-p9.c b/hw/sbe-p9.c index a9810a1..5c63ec1 100644 --- a/hw/sbe-p9.c +++ b/hw/sbe-p9.c @@ -40,6 +40,7 @@ #include <errorlog.h> #include <lock.h> #include <opal.h> +#include <opal-dump.h> #include <sbe-p9.h> #include <skiboot.h> #include <timebase.h> @@ -951,6 +952,9 @@ void p9_sbe_terminate(void) if (!dt_find_by_path(opal_node, "dump")) return; + /* Save crashing CPU details */ + opal_mpipl_save_crashing_pir(); + /* * Send S0 interrupt to all SBE. Sequence: * - S0 interrupt on secondary chip SBE diff --git a/include/opal-dump.h b/include/opal-dump.h index e115382..866d11a 100644 --- a/include/opal-dump.h +++ b/include/opal-dump.h @@ -121,4 +121,7 @@ struct mpipl_metadata { /* init opal dump */ extern void opal_mpipl_init(void); +/* Save metadata before triggering MPIPL */ +void opal_mpipl_save_crashing_pir(void); + #endif /* __OPAL_DUMP_H */ |