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| author | Reza Arbab <arbab@linux.ibm.com> | 2019-08-05 15:33:27 -0500 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2019-08-16 15:51:55 +1000 |
| commit | 82b576886fd6d2bda3e27b0949a972c18b5a9fbf (patch) | |
| tree | 63e0e30f2e7ff2e40129f9a509c2d2c11e4193b9 | |
| parent | 3e334fbb85417da0dae045fcec350efc3dae206b (diff) | |
| download | skiboot-82b576886fd6d2bda3e27b0949a972c18b5a9fbf.zip skiboot-82b576886fd6d2bda3e27b0949a972c18b5a9fbf.tar.gz skiboot-82b576886fd6d2bda3e27b0949a972c18b5a9fbf.tar.bz2 | |
npu3: Initialize NPU3_SNP_MISC_CFG0
Enable powerbus snooping here, or else MMIO to any NTL/NDL registers
will cause a checkstop.
This was not an issue in Simics simulation, but discovered rather
quickly during bringup on a real Axone chip.
Signed-off-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Christophe Lombard <clombard@linux.vnet.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
| -rw-r--r-- | hw/npu3.c | 7 | ||||
| -rw-r--r-- | include/npu3-regs.h | 4 |
2 files changed, 11 insertions, 0 deletions
@@ -309,6 +309,13 @@ static void npu3_misc_config(struct npu3 *npu) val = SETFIELD(NPU3_MCP_MISC_CFG0_OCAPI_MODE, val, ~typemap); npu3_write(npu, reg, val); + reg = NPU3_SNP_MISC_CFG0; + val = npu3_read(npu, reg); + val |= NPU3_SNP_MISC_CFG0_ENABLE_PBUS; + val = SETFIELD(NPU3_SNP_MISC_CFG0_NVLINK_MODE, val, typemap); + val = SETFIELD(NPU3_SNP_MISC_CFG0_OCAPI_MODE, val, ~typemap); + npu3_write(npu, reg, val); + reg = NPU3_CTL_MISC_CFG2; val = npu3_read(npu, reg); val = SETFIELD(NPU3_CTL_MISC_CFG2_NVLINK_MODE, val, typemap); diff --git a/include/npu3-regs.h b/include/npu3-regs.h index c0c7eab..341d652 100644 --- a/include/npu3-regs.h +++ b/include/npu3-regs.h @@ -93,6 +93,10 @@ #define NPU3_MCP_MISC_CFG0_NVLINK_MODE PPC_BITMASK(49, 53) #define NPU3_MCP_MISC_CFG1 (NPU3_BLOCK_CQ_SM(0) + 0x008) #define NPU3_MCP_MISC_CFG2 (NPU3_BLOCK_CQ_SM(0) + 0x0f0) +#define NPU3_SNP_MISC_CFG0 (NPU3_BLOCK_CQ_SM(0) + 0x180) +#define NPU3_SNP_MISC_CFG0_ENABLE_PBUS PPC_BIT(2) +#define NPU3_SNP_MISC_CFG0_OCAPI_MODE PPC_BITMASK(32, 36) +#define NPU3_SNP_MISC_CFG0_NVLINK_MODE PPC_BITMASK(37, 41) #define NPU3_GPU_MEM_BAR(brk) (NPU3_BLOCK_CQ_SM(0) + 0x190 + (brk) * 8) #define NPU3_GPU_MEM_BAR_ENABLE PPC_BIT(0) #define NPU3_GPU_MEM_BAR_ADDR_MASK PPC_BITMASK(1, 35) |