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| author | Stewart Smith <stewart@flamingspork.com> | 2021-12-17 12:36:44 +1000 |
|---|---|---|
| committer | Cédric Le Goater <clg@kaod.org> | 2021-12-17 10:34:23 +0100 |
| commit | b3371e08aff874acb56724f1f2bc5babbd3c58f1 (patch) | |
| tree | ee8d3c0546fe3a850a39ff3b60d51ab8e34757cc | |
| parent | f9a19f3d2add0166d2f380eb0c25a94f0da80d8b (diff) | |
| download | skiboot-b3371e08aff874acb56724f1f2bc5babbd3c58f1.zip skiboot-b3371e08aff874acb56724f1f2bc5babbd3c58f1.tar.gz skiboot-b3371e08aff874acb56724f1f2bc5babbd3c58f1.tar.bz2 | |
npu: move npu_set_fence_state() to phb_ops
This lets us consider not building in npu.o
Reviewed-by: Dan Horák <dan@danny.cz>
Signed-off-by: Stewart Smith <stewart@flamingspork.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
| -rw-r--r-- | core/hmi.c | 2 | ||||
| -rw-r--r-- | hw/npu.c | 7 | ||||
| -rw-r--r-- | include/npu.h | 1 | ||||
| -rw-r--r-- | include/pci.h | 3 |
4 files changed, 9 insertions, 4 deletions
@@ -908,7 +908,7 @@ static void find_npu_checkstop_reason(int flat_chip_id, if (phb->phb_type == phb_type_pcie_v3) { /* Set the NPU to fenced since it can't recover. */ - npu_set_fence_state(phb_to_npu(phb), true); + phb->ops->set_fence_state(phb, true); } /* Set up the HMI event */ @@ -925,7 +925,9 @@ static int64_t npu_eeh_next_error(struct phb *phb, } /* For use in error injection and handling. */ -void npu_set_fence_state(struct npu *p, bool fence) { +static void npu_set_fence_state(struct phb *phb, bool fence) { + struct npu *p = phb_to_npu(phb); + p->fenced = fence; if (fence) @@ -968,7 +970,7 @@ static int64_t npu_err_inject(struct phb *phb, uint64_t pe_number, return OPAL_PARAMETER; } else if (type == 1) { /* Emulate fence mode. */ - npu_set_fence_state(p, true); + npu_set_fence_state(phb, true); } else { /* Cause a freeze with an invalid MMIO read. If the BAR is not * enabled, this will checkstop the machine. @@ -1012,6 +1014,7 @@ static const struct phb_ops npu_ops = { .get_diag_data2 = NULL, .set_capi_mode = NULL, .set_capp_recovery = NULL, + .set_fence_state = npu_set_fence_state, }; static void assign_mmio_bars(uint32_t gcid, uint32_t xscom, diff --git a/include/npu.h b/include/npu.h index 50cc9c9..45818a2 100644 --- a/include/npu.h +++ b/include/npu.h @@ -153,7 +153,6 @@ int64_t npu_dev_procedure(void *dev, struct pci_cfg_reg_filter *pcrf, uint32_t offset, uint32_t len, uint32_t *data, bool write); -void npu_set_fence_state(struct npu *p, bool fence); void npu_dev_procedure_reset(struct npu_dev *dev); #define NPUDBG(p, fmt, a...) prlog(PR_DEBUG, "NPU%d: " fmt, \ diff --git a/include/pci.h b/include/pci.h index caae744..1014424 100644 --- a/include/pci.h +++ b/include/pci.h @@ -340,6 +340,9 @@ struct phb_ops { /* Get/set PBCQ Tunnel BAR register */ void (*get_tunnel_bar)(struct phb *phb, uint64_t *addr); int64_t (*set_tunnel_bar)(struct phb *phb, uint64_t addr); + + /* Currently only used by NPU HMI code */ + void (*set_fence_state)(struct phb *phb, bool fence); }; enum phb_type { |