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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-01-29 10:22:07 +0100 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-09-28 14:22:07 +0530 |
| commit | cb730dc63c28830c8a20966b67515240bfc778fd (patch) | |
| tree | 0b2e4e59a4ec046725ea34a52787ba5e03d9ddf3 | |
| parent | 74a7a87a43ad55aff019ca8d98bea406fee1e125 (diff) | |
| download | skiboot-cb730dc63c28830c8a20966b67515240bfc778fd.zip skiboot-cb730dc63c28830c8a20966b67515240bfc778fd.tar.gz skiboot-cb730dc63c28830c8a20966b67515240bfc778fd.tar.bz2 | |
phb4: Disable TCE cache line buffer
[ Upstream commit 15b93a301509ba7813343540e25b47ba395674b9 ]
This patch implements a circumvention for HW557787. It disables the
TCE cache line buffer as, under heavy loads, there's a possibility of
an entry being re-allocated incorrectly.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 1 | ||||
| -rw-r--r-- | include/phb4-regs.h | 1 |
2 files changed, 2 insertions, 0 deletions
@@ -5192,6 +5192,7 @@ static void phb4_init_hw(struct phb4 *p) /* Init_17 - PHB Control */ val = PHB_CTRLR_IRQ_PGSZ_64K; + val |= PHB_CTRLR_TCE_CLB_DISABLE; // HW557787 circumvention val |= SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_2_PER_PE); if (PHB4_CAN_STORE_EOI(p)) val |= PHB_CTRLR_IRQ_STORE_EOI; diff --git a/include/phb4-regs.h b/include/phb4-regs.h index d2fc357..979ae19 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -110,6 +110,7 @@ #define TVT_4_PER_PE 1 #define TVT_8_PER_PE 2 #define TVT_16_PER_PE 3 +#define PHB_CTRLR_TCE_CLB_DISABLE PPC_BIT(21) #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28,31) #define PHB_AIB_FENCE_CTRL 0x860 #define PHB_TCE_TAG_ENABLE 0x868 |