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| author | Nicholas Piggin <npiggin@gmail.com> | 2021-10-03 11:22:06 +1000 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-10-19 12:08:19 +0530 |
| commit | f9a40dea2bd7bc44440f9c0c5e8c90c3fd7559eb (patch) | |
| tree | f4873c99162d14e55c20276d1d47eacd71069d5a | |
| parent | b30fb5365fe21f60de13d08bd50524f1ead8fe54 (diff) | |
| download | skiboot-f9a40dea2bd7bc44440f9c0c5e8c90c3fd7559eb.zip skiboot-f9a40dea2bd7bc44440f9c0c5e8c90c3fd7559eb.tar.gz skiboot-f9a40dea2bd7bc44440f9c0c5e8c90c3fd7559eb.tar.bz2 | |
asm/head: Fix P10 HILE for little endian build
Fixes: 891ed8df67 ("Initial POWER10 enablement")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | asm/head.S | 5 |
1 files changed, 5 insertions, 0 deletions
@@ -829,8 +829,13 @@ init_shared_sprs: /* HID0: * Boot with PPC_BIT(5) set (dis_recovery). * Leave bit 5 set to disable recovery (due to HW570622) + * Set/clear bit 4 (HILE) depending on skiboot endian */ +#if HAVE_BIG_ENDIAN LOAD_IMM64(%r3, PPC_BIT(5)) +#else + LOAD_IMM64(%r3, PPC_BIT(5) | PPC_BIT(4)) +#endif sync mtspr SPR_HID0,%r3 isync |