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| author | Mahesh Salgaonkar <mahesh@linux.ibm.com> | 2021-02-09 14:14:11 +0530 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-06-24 16:59:50 +0530 |
| commit | 2d593ddd7f1221010e1459765e7b17807d2b0896 (patch) | |
| tree | 42203e399cf4282ca6692d3c69326c6473ed7af5 | |
| parent | 812621a1de92714df05366707fa6986b503cadaf (diff) | |
| download | skiboot-2d593ddd7f1221010e1459765e7b17807d2b0896.zip skiboot-2d593ddd7f1221010e1459765e7b17807d2b0896.tar.gz skiboot-2d593ddd7f1221010e1459765e7b17807d2b0896.tar.bz2 | |
phb4: Avoid MMIO load freeze escalation on every chip
[ Upstream commit d51eb6f95e7078235ba2217e2dc9fc53e65bc902 ]
The commit f397cc30bdf8 ("phb4: Only escalate freezes on MMIO load where
necessary") introduced a change to restrict escalation to the chips that
actually need it. However it missed one case which still causes the
escalation on every chip. This affects EEH recovery to cause full
PHB reset on some chips which is not necessary. This patch fixes that.
Also, add a check for p9 chip in phb4_escalation_required() function.
Cc: skiboot-stable@lists.ozlabs.org
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | hw/phb4.c | 6 |
1 files changed, 5 insertions, 1 deletions
@@ -3590,6 +3590,10 @@ static bool phb4_escalation_required(void) { uint64_t pvr = mfspr(SPR_PVR); + /* Only on Power9 */ + if (proc_gen != proc_gen_p9) + return false; + /* * Escalation is required on the following chip versions: * - Cumulus DD1.0 @@ -3850,7 +3854,7 @@ static int64_t phb4_eeh_next_error(struct phb *phb, if (*first_frozen_pe != (uint64_t)(-1)) { pesta = phb4_get_pesta(p, *first_frozen_pe); - if (phb4_freeze_escalate(pesta)) { + if (phb4_escalation_required() && phb4_freeze_escalate(pesta)) { PHBINF(p, "Escalating freeze to fence. PESTA[%lli]=%016llx\n", *first_frozen_pe, pesta); p->err.err_class = PHB4_ERR_CLASS_FENCED; |