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| author | Nicholas Piggin <npiggin@gmail.com> | 2020-09-10 02:29:46 +1000 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2020-10-22 16:33:38 +0530 |
| commit | 5c976aeb5a1b6c39a0fe526f912f1d241aa9fbf4 (patch) | |
| tree | ff58fac04249471531761d306937422479d34dd8 | |
| parent | 88a6dc9ecc15d13d56d59da6b0d300dc03075912 (diff) | |
| download | skiboot-5c976aeb5a1b6c39a0fe526f912f1d241aa9fbf4.zip skiboot-5c976aeb5a1b6c39a0fe526f912f1d241aa9fbf4.tar.gz skiboot-5c976aeb5a1b6c39a0fe526f912f1d241aa9fbf4.tar.bz2 | |
asm/head: fix power save wakeup register corruption
[ Upstream commit 355a7dc193292b5b543e1bba1ff8b4a295fe8381 ]
Power save wakeup handlers can clobber r30 before testing for state
loss and avoiding restoring non-volatile GPRs. Fix this by using r5
instead (and move the register usage to one place, for clarity).
Cc: skiboot-stable@lists.ozlabs.org
Fixes: 8a43bf86b7 ("core/exceptions: implement an exception handler for non-powersave sresets")
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
| -rw-r--r-- | asm/head.S | 8 |
1 files changed, 4 insertions, 4 deletions
@@ -114,7 +114,6 @@ hdat_entry: li %r4,0x200 b _exception 1: - LOAD_IMM64(%r30, SKIBOOT_BASE) cmpdi %r3,0x1 bne 2f /* state loss */ LOAD_IMM32(%r3, reset_resume - __head) @@ -122,7 +121,8 @@ hdat_entry: 2: LOAD_IMM32(%r3, reset_wakeup - __head) 3: - add %r3,%r30,%r3 + LOAD_IMM64(%r5, SKIBOOT_BASE) + add %r3,%r5,%r3 mtctr %r3 li %r3,0x200 bctr @@ -567,7 +567,6 @@ reset_patch_start: li %r4,0x100 b _exception + (reset_patch_start - sreset_vector) 1: - LOAD_IMM64(%r30, SKIBOOT_BASE) cmpdi %r3,0x1 bne 2f /* state loss */ LOAD_IMM32(%r3, reset_resume - __head) @@ -575,7 +574,8 @@ reset_patch_start: 2: LOAD_IMM32(%r3, reset_wakeup - __head) 3: - add %r3,%r30,%r3 + LOAD_IMM64(%r5, SKIBOOT_BASE) + add %r3,%r5,%r3 mtctr %r3 li %r3,0x100 bctr |