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| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2020-01-22 16:03:34 +0100 |
|---|---|---|
| committer | Oliver O'Halloran <oohall@gmail.com> | 2020-01-29 13:51:35 +1100 |
| commit | 57d43efd6bbb052b467df3a19ca84feccdd0649b (patch) | |
| tree | 2f5e7b8edd68207ed69bc36a44201fa6e91b8237 | |
| parent | da28a6642b79a68d6c8773f149692a3702a31240 (diff) | |
| download | skiboot-57d43efd6bbb052b467df3a19ca84feccdd0649b.zip skiboot-57d43efd6bbb052b467df3a19ca84feccdd0649b.tar.gz skiboot-57d43efd6bbb052b467df3a19ca84feccdd0649b.tar.bz2 | |
npu3: Don't use the device tree to assign the phb-index of the PHB
On Axone, there's a 1-to-1 mapping between virtual PHBs and NPUs. We
could keep assigning the phb-index of the virtual PHB from the value
found in the npu node of the device tree, but to be consistent with
P9/npu2 and avoid confusion, this patch assigns the phb-index when the
virtual PHB is created, based on the npu index, similarly to what we
do on P9.
Reviewed-by: Reza Arbab <arbab@linux.ibm.com>
Reviewed-by: Andrew Donnellan <ajd@linux.ibm.com>
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
| -rw-r--r-- | hw/npu3-nvlink.c | 2 | ||||
| -rw-r--r-- | include/npu3.h | 6 |
2 files changed, 7 insertions, 1 deletions
diff --git a/hw/npu3-nvlink.c b/hw/npu3-nvlink.c index 9630158..b8856dd 100644 --- a/hw/npu3-nvlink.c +++ b/hw/npu3-nvlink.c @@ -1478,7 +1478,7 @@ static void npu3_dt_add_props(struct npu3 *npu) "ibm,ioda2-npu3-phb"); dt_add_property_cells(dn, "ibm,phb-index", - dt_prop_get_u32(npu->dt_node, "ibm,phb-index")); + npu3_get_phb_index(npu->index)); dt_add_property_cells(dn, "ibm,phb-diag-data-size", 0); dt_add_property_cells(dn, "ibm,opal-num-pes", NPU3_MAX_PE_NUM); dt_add_property_cells(dn, "ibm,opal-reserved-pe", NPU3_RESERVED_PE_NUM); diff --git a/include/npu3.h b/include/npu3.h index 1c657f9..0fdad4d 100644 --- a/include/npu3.h +++ b/include/npu3.h @@ -177,4 +177,10 @@ int64_t npu3_map_lpar(struct phb *phb, uint64_t bdf, uint64_t lparid, int64_t npu3_set_relaxed_order(struct phb *phb, uint32_t gcid, int pec, bool enable); +#define NPU3_PHB_INDEX_BASE 6 /* immediately after real PHBs */ +static inline int npu3_get_phb_index(unsigned int npu_index) +{ + return NPU3_PHB_INDEX_BASE + npu_index; +} + #endif /* __NPU3_H */ |