diff options
| author | Frederic Barrat <fbarrat@linux.ibm.com> | 2021-01-29 10:22:07 +0100 |
|---|---|---|
| committer | Vasant Hegde <hegdevasant@linux.vnet.ibm.com> | 2021-09-30 16:05:16 +0530 |
| commit | 669aa5efffd15cd584b721de55c98f8e670d4599 (patch) | |
| tree | 2a22d341f32c211bddf16f2aea8b5f6af58efd3d | |
| parent | aec65d45470cff3f33f8005b599ccb4a359bf72c (diff) | |
| download | skiboot-669aa5efffd15cd584b721de55c98f8e670d4599.zip skiboot-669aa5efffd15cd584b721de55c98f8e670d4599.tar.gz skiboot-669aa5efffd15cd584b721de55c98f8e670d4599.tar.bz2 | |
phb4: Disable TCE cache line buffer
[ Upstream commit 15b93a301509ba7813343540e25b47ba395674b9 ]
This patch implements a circumvention for HW557787. It disables the
TCE cache line buffer as, under heavy loads, there's a possibility of
an entry being re-allocated incorrectly.
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
Signed-off-by: Vasant Hegde <hegdevasant@linux.vnet.ibm.com>
[FB]: adjust due to branch supporting DD1
Signed-off-by: Frederic Barrat <fbarrat@linux.ibm.com>
| -rw-r--r-- | hw/phb4.c | 1 | ||||
| -rw-r--r-- | include/phb4-regs.h | 1 |
2 files changed, 2 insertions, 0 deletions
@@ -4822,6 +4822,7 @@ static void phb4_init_hw(struct phb4 *p, bool first_init) /* Init_17 - PHB Control */ val = PHB_CTRLR_IRQ_PGSZ_64K; + val |= PHB_CTRLR_TCE_CLB_DISABLE; // HW557787 circumvention if (p->rev == PHB4_REV_NIMBUS_DD10) { val |= SETFIELD(PHB_CTRLR_TVT_ADDR_SEL, 0ull, TVT_DD1_2_PER_PE); } else { diff --git a/include/phb4-regs.h b/include/phb4-regs.h index 28f22f9..490e1d7 100644 --- a/include/phb4-regs.h +++ b/include/phb4-regs.h @@ -144,6 +144,7 @@ #define TVT_4_PER_PE 1 #define TVT_8_PER_PE 2 #define TVT_16_PER_PE 3 +#define PHB_CTRLR_TCE_CLB_DISABLE PPC_BIT(21) #define PHB_CTRLR_DMA_RD_SPACING PPC_BITMASK(28,31) #define PHB_AIB_FENCE_CTRL 0x860 #define PHB_TCE_TAG_ENABLE 0x868 |