pci: make PCI slot state as incremental to base number

Various backends define their own PCI slot states for flexibility
with numbers [A]. PCI core also defines its PCI slot states [B].
For one specific PCI slot state, the major number of [A] and [B]
should be same so that the corresponding operation can be found.
It means [A] and [B] are relevant to some extent, but the code
where defines the PCI slots in backends doesn't reflect it.

This makes the major PCI slot state defined in backend same to
the corresponding one defined in PCI core. The minor PCI slot
states are made to be incremental to their base number (major
PCI slot state). No functional changes introduced.

Signed-off-by: Gavin Shan <gwshan@linux.vnet.ibm.com>
Acked-by: Russell Currey <ruscur@russell.cc>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

5 files changed, 93 insertions, 93 deletions

diff --git a/include/p7ioc.h b/include/p7ioc.h
index 3b57a9c..ab19945 100644
--- a/include/p7ioc.h
+++ b/include/p7ioc.h
@@ -209,26 +209,26 @@ enum p7ioc_phb_state {
 };
 
 /* P7IOC PHB slot states */
-#define P7IOC_SLOT_NORMAL		0x00000000
-#define P7IOC_SLOT_LINK			0x00000100
-#define   P7IOC_SLOT_LINK_START		0x00000101
-#define   P7IOC_SLOT_LINK_WAIT		0x00000102
-#define P7IOC_SLOT_HRESET		0x00000200
-#define   P7IOC_SLOT_HRESET_START	0x00000201
-#define   P7IOC_SLOT_HRESET_TRAINING	0x00000202
-#define   P7IOC_SLOT_HRESET_DELAY	0x00000203
-#define   P7IOC_SLOT_HRESET_DELAY2	0x00000204
-#define P7IOC_SLOT_FRESET		0x00000300
-#define   P7IOC_SLOT_FRESET_START	0x00000301
-#define   P7IOC_SLOT_FRESET_TRAINING	0x00000302
-#define   P7IOC_SLOT_FRESET_POWER_OFF	0x00000303
-#define   P7IOC_SLOT_FRESET_POWER_ON	0x00000304
-#define   P7IOC_SLOT_FRESET_ASSERT	0x00000305
-#define   P7IOC_SLOT_FRESET_DEASSERT	0x00000306
-#define P7IOC_SLOT_PFRESET		0x00000400
-#define   P7IOC_SLOT_PFRESET_START	0x00000401
-#define P7IOC_SLOT_CRESET		0x00000500
-#define   P7IOC_SLOT_CRESET_START	0x00000501
+#define P7IOC_SLOT_NORMAL		PCI_SLOT_STATE_NORMAL
+#define P7IOC_SLOT_LINK			PCI_SLOT_STATE_LINK
+#define   P7IOC_SLOT_LINK_START		(P7IOC_SLOT_LINK + 1)
+#define   P7IOC_SLOT_LINK_WAIT		(P7IOC_SLOT_LINK + 2)
+#define P7IOC_SLOT_HRESET		PCI_SLOT_STATE_HRESET
+#define   P7IOC_SLOT_HRESET_START	(P7IOC_SLOT_HRESET + 1)
+#define   P7IOC_SLOT_HRESET_TRAINING	(P7IOC_SLOT_HRESET + 2)
+#define   P7IOC_SLOT_HRESET_DELAY	(P7IOC_SLOT_HRESET + 3)
+#define   P7IOC_SLOT_HRESET_DELAY2	(P7IOC_SLOT_HRESET + 4)
+#define P7IOC_SLOT_FRESET		PCI_SLOT_STATE_FRESET
+#define   P7IOC_SLOT_FRESET_START	(P7IOC_SLOT_FRESET + 1)
+#define   P7IOC_SLOT_FRESET_TRAINING	(P7IOC_SLOT_FRESET + 2)
+#define   P7IOC_SLOT_FRESET_POWER_OFF	(P7IOC_SLOT_FRESET + 3)
+#define   P7IOC_SLOT_FRESET_POWER_ON	(P7IOC_SLOT_FRESET + 4)
+#define   P7IOC_SLOT_FRESET_ASSERT	(P7IOC_SLOT_FRESET + 5)
+#define   P7IOC_SLOT_FRESET_DEASSERT	(P7IOC_SLOT_FRESET + 6)
+#define P7IOC_SLOT_PFRESET		PCI_SLOT_STATE_PFRESET
+#define   P7IOC_SLOT_PFRESET_START	(P7IOC_SLOT_PFRESET + 1)
+#define P7IOC_SLOT_CRESET		PCI_SLOT_STATE_CRESET
+#define   P7IOC_SLOT_CRESET_START	(P7IOC_SLOT_CRESET + 1)
 
 /*
  * In order to support error detection and recovery on different
diff --git a/include/pci-slot.h b/include/pci-slot.h
index 694a448..f7634b8 100644
--- a/include/pci-slot.h
+++ b/include/pci-slot.h
@@ -125,25 +125,25 @@ struct pci_slot_ops {
 #define PCI_SLOT_STATE_MASK			0xFFFFFF00
 #define PCI_SLOT_STATE_NORMAL			0x00000000
 #define PCI_SLOT_STATE_LINK			0x00000100
-#define   PCI_SLOT_STATE_LINK_START_POLL	0x00000101
-#define   PCI_SLOT_STATE_LINK_DELAY_FINALIZED	0x00000102
-#define   PCI_SLOT_STATE_LINK_POLLING		0x00000103
+#define   PCI_SLOT_STATE_LINK_START_POLL	(PCI_SLOT_STATE_LINK + 1)
+#define   PCI_SLOT_STATE_LINK_DELAY_FINALIZED	(PCI_SLOT_STATE_LINK + 2)
+#define   PCI_SLOT_STATE_LINK_POLLING		(PCI_SLOT_STATE_LINK + 3)
 #define PCI_SLOT_STATE_HRESET			0x00000200
-#define   PCI_SLOT_STATE_HRESET_START		0x00000201
-#define   PCI_SLOT_STATE_HRESET_HOLD		0x00000202
+#define   PCI_SLOT_STATE_HRESET_START		(PCI_SLOT_STATE_HRESET + 1)
+#define   PCI_SLOT_STATE_HRESET_HOLD		(PCI_SLOT_STATE_HRESET + 2)
 #define PCI_SLOT_STATE_FRESET			0x00000300
-#define   PCI_SLOT_STATE_FRESET_POWER_OFF	0x00000301
+#define   PCI_SLOT_STATE_FRESET_POWER_OFF	(PCI_SLOT_STATE_FRESET + 1)
 #define PCI_SLOT_STATE_PFRESET			0x00000400
-#define   PCI_SLOT_STATE_PFRESET_START		0x00000401
+#define   PCI_SLOT_STATE_PFRESET_START		(PCI_SLOT_STATE_PFRESET + 1)
 #define PCI_SLOT_STATE_CRESET			0x00000500
-#define   PCI_SLOT_STATE_CRESET_START		0x00000501
+#define   PCI_SLOT_STATE_CRESET_START		(PCI_SLOT_STATE_CRESET + 1)
 #define PCI_SLOT_STATE_GPOWER			0x00000600
-#define   PCI_SLOT_STATE_GPOWER_START		0x00000601
+#define   PCI_SLOT_STATE_GPOWER_START		(PCI_SLOT_STATE_GPOWER + 1)
 #define PCI_SLOT_STATE_SPOWER			0x00000700
-#define   PCI_SLOT_STATE_SPOWER_START		0x00000701
-#define   PCI_SLOT_STATE_SPOWER_DONE		0x00000702
+#define   PCI_SLOT_STATE_SPOWER_START		(PCI_SLOT_STATE_SPOWER + 1)
+#define   PCI_SLOT_STATE_SPOWER_DONE		(PCI_SLOT_STATE_SPOWER + 2)
 #define PCI_SLOT_STATE_GPRESENCE		0x00000800
-#define   PCI_SLOT_STATE_GPRESENCE_START	0x00000801
+#define   PCI_SLOT_STATE_GPRESENCE_START	(PCI_SLOT_STATE_GPRESENCE + 1)
 
 
 struct pci_slot {
diff --git a/include/phb3.h b/include/phb3.h
index cf4b910..dbf3c38 100644
--- a/include/phb3.h
+++ b/include/phb3.h
@@ -211,26 +211,26 @@ enum phb3_state {
  * changes here, please make sure the base state isn't
  * conflicting with those defined in pci-slot.h
  */
-#define PHB3_SLOT_NORMAL			0x00000000
-#define PHB3_SLOT_LINK				0x00000100
-#define   PHB3_SLOT_LINK_START			0x00000101
-#define   PHB3_SLOT_LINK_WAIT_ELECTRICAL	0x00000102
-#define   PHB3_SLOT_LINK_WAIT			0x00000103
-#define PHB3_SLOT_HRESET			0x00000200
-#define   PHB3_SLOT_HRESET_START		0x00000201
-#define   PHB3_SLOT_HRESET_DELAY		0x00000202
-#define   PHB3_SLOT_HRESET_DELAY2		0x00000203
-#define PHB3_SLOT_FRESET			0x00000300
-#define   PHB3_SLOT_FRESET_START		0x00000301
-#define PHB3_SLOT_PFRESET			0x00000400
-#define   PHB3_SLOT_PFRESET_START		0x00000401
-#define   PHB3_SLOT_PFRESET_ASSERT_DELAY	0x00000402
-#define   PHB3_SLOT_PFRESET_DEASSERT_DELAY	0x00000403
-#define PHB3_SLOT_CRESET			0x00000500
-#define   PHB3_SLOT_CRESET_START		0x00000501
-#define   PHB3_SLOT_CRESET_WAIT_CQ		0x00000502
-#define   PHB3_SLOT_CRESET_REINIT		0x00000503
-#define   PHB3_SLOT_CRESET_FRESET		0x00000504
+#define PHB3_SLOT_NORMAL			PCI_SLOT_STATE_NORMAL
+#define PHB3_SLOT_LINK				PCI_SLOT_STATE_LINK
+#define   PHB3_SLOT_LINK_START			(PHB3_SLOT_LINK + 1)
+#define   PHB3_SLOT_LINK_WAIT_ELECTRICAL	(PHB3_SLOT_LINK + 2)
+#define   PHB3_SLOT_LINK_WAIT			(PHB3_SLOT_LINK + 3)
+#define PHB3_SLOT_HRESET			PCI_SLOT_STATE_HRESET
+#define   PHB3_SLOT_HRESET_START		(PHB3_SLOT_HRESET + 1)
+#define   PHB3_SLOT_HRESET_DELAY		(PHB3_SLOT_HRESET + 2)
+#define   PHB3_SLOT_HRESET_DELAY2		(PHB3_SLOT_HRESET + 3)
+#define PHB3_SLOT_FRESET			PCI_SLOT_STATE_FRESET
+#define   PHB3_SLOT_FRESET_START		(PHB3_SLOT_FRESET + 1)
+#define PHB3_SLOT_PFRESET			PCI_SLOT_STATE_PFRESET
+#define   PHB3_SLOT_PFRESET_START		(PHB3_SLOT_PFRESET + 1)
+#define   PHB3_SLOT_PFRESET_ASSERT_DELAY	(PHB3_SLOT_PFRESET + 2)
+#define   PHB3_SLOT_PFRESET_DEASSERT_DELAY	(PHB3_SLOT_PFRESET + 3)
+#define PHB3_SLOT_CRESET			PCI_SLOT_STATE_CRESET
+#define   PHB3_SLOT_CRESET_START		(PHB3_SLOT_CRESET + 1)
+#define   PHB3_SLOT_CRESET_WAIT_CQ		(PHB3_SLOT_CRESET + 2)
+#define   PHB3_SLOT_CRESET_REINIT		(PHB3_SLOT_CRESET + 3)
+#define   PHB3_SLOT_CRESET_FRESET		(PHB3_SLOT_CRESET + 4)
 
 /*
  * PHB3 error descriptor. Errors from all components (PBCQ, PHB)
diff --git a/include/phb4.h b/include/phb4.h
index 9b73edb..fb23d0f 100644
--- a/include/phb4.h
+++ b/include/phb4.h
@@ -172,26 +172,26 @@ enum phb4_state {
  * changes here, please make sure the base state isn't
  * conflicting with those defined in pci-slot.h
  */
-#define PHB4_SLOT_NORMAL			0x00000000
-#define PHB4_SLOT_LINK				0x00000100
-#define   PHB4_SLOT_LINK_START			0x00000101
-#define   PHB4_SLOT_LINK_WAIT_ELECTRICAL	0x00000102
-#define   PHB4_SLOT_LINK_WAIT			0x00000103
-#define PHB4_SLOT_HRESET			0x00000200
-#define   PHB4_SLOT_HRESET_START		0x00000201
-#define   PHB4_SLOT_HRESET_DELAY		0x00000202
-#define   PHB4_SLOT_HRESET_DELAY2		0x00000203
-#define PHB4_SLOT_FRESET			0x00000300
-#define   PHB4_SLOT_FRESET_START		0x00000301
-#define PHB4_SLOT_PFRESET			0x00000400
-#define   PHB4_SLOT_PFRESET_START		0x00000401
-#define   PHB4_SLOT_PFRESET_ASSERT_DELAY	0x00000402
-#define   PHB4_SLOT_PFRESET_DEASSERT_DELAY	0x00000403
-#define PHB4_SLOT_CRESET			0x00000500
-#define   PHB4_SLOT_CRESET_START		0x00000501
-#define   PHB4_SLOT_CRESET_WAIT_CQ		0x00000502
-#define   PHB4_SLOT_CRESET_REINIT		0x00000503
-#define   PHB4_SLOT_CRESET_FRESET		0x00000504
+#define PHB4_SLOT_NORMAL			PCI_SLOT_STATE_NORMAL
+#define PHB4_SLOT_LINK				PCI_SLOT_STATE_LINK
+#define   PHB4_SLOT_LINK_START			(PHB4_SLOT_LINK + 1)
+#define   PHB4_SLOT_LINK_WAIT_ELECTRICAL	(PHB4_SLOT_LINK + 2)
+#define   PHB4_SLOT_LINK_WAIT			(PHB4_SLOT_LINK + 3)
+#define PHB4_SLOT_HRESET			PCI_SLOT_STATE_HRESET
+#define   PHB4_SLOT_HRESET_START		(PHB4_SLOT_HRESET + 1)
+#define   PHB4_SLOT_HRESET_DELAY		(PHB4_SLOT_HRESET + 2)
+#define   PHB4_SLOT_HRESET_DELAY2		(PHB4_SLOT_HRESET + 3)
+#define PHB4_SLOT_FRESET			PCI_SLOT_STATE_FRESET
+#define   PHB4_SLOT_FRESET_START		(PHB4_SLOT_FRESET + 1)
+#define PHB4_SLOT_PFRESET			PCI_SLOT_STATE_PFRESET
+#define   PHB4_SLOT_PFRESET_START		(PHB4_SLOT_PFRESET + 1)
+#define   PHB4_SLOT_PFRESET_ASSERT_DELAY	(PHB4_SLOT_PFRESET + 2)
+#define   PHB4_SLOT_PFRESET_DEASSERT_DELAY	(PHB4_SLOT_PFRESET + 3)
+#define PHB4_SLOT_CRESET			PCI_SLOT_STATE_CRESET
+#define   PHB4_SLOT_CRESET_START		(PHB4_SLOT_CRESET + 1)
+#define   PHB4_SLOT_CRESET_WAIT_CQ		(PHB4_SLOT_CRESET + 2)
+#define   PHB4_SLOT_CRESET_REINIT		(PHB4_SLOT_CRESET + 3)
+#define   PHB4_SLOT_CRESET_FRESET		(PHB4_SLOT_CRESET + 4)
 
 /*
  * PHB4 error descriptor. Errors from all components (PBCQ, PHB)
diff --git a/platforms/ibm-fsp/firenze-pci.c b/platforms/ibm-fsp/firenze-pci.c
index 2b8c0c6..ff14a4c 100644
--- a/platforms/ibm-fsp/firenze-pci.c
+++ b/platforms/ibm-fsp/firenze-pci.c
@@ -39,27 +39,27 @@
  * Refer to pci-slot.h for the default PCI state set
  * when you're going to change below values.
  */
-#define FIRENZE_PCI_SLOT_NORMAL			0x00000000
-#define FIRENZE_PCI_SLOT_LINK			0x00000100
-#define   FIRENZE_PCI_SLOT_LINK_START		0x00000101
-#define FIRENZE_PCI_SLOT_HRESET			0x00000200
-#define   FIRENZE_PCI_SLOT_HRESET_START		0x00000201
-#define FIRENZE_PCI_SLOT_FRESET			0x00000300
-#define FIRENZE_PCI_SLOT_FRESET_START		0x00000301
-#define   FIRENZE_PCI_SLOT_FRESET_WAIT_RSP	0x00000302
-#define   FIRENZE_PCI_SLOT_FRESET_DELAY		0x00000303
-#define   FIRENZE_PCI_SLOT_FRESET_POWER_STATE	0x00000304
-#define   FIRENZE_PCI_SLOT_FRESET_POWER_OFF	0x00000305
-#define   FIRENZE_PCI_SLOT_FRESET_POWER_ON	0x00000306
-#define   FIRENZE_PCI_SLOT_PERST_DEASSERT	0x00000307
-#define   FIRENZE_PCI_SLOT_PERST_DELAY		0x00000308
-#define FIRENZE_PCI_SLOT_PFRESET		0x00000400
-#define   FIRENZE_PCI_SLOT_PFRESET_START	0x00000401
-#define FIRENZE_PCI_SLOT_GPOWER			0x00000600
-#define   FIRENZE_PCI_SLOT_GPOWER_START		0x00000601
-#define FIRENZE_PCI_SLOT_SPOWER			0x00000700
-#define   FIRENZE_PCI_SLOT_SPOWER_START		0x00000701
-#define   FIRENZE_PCI_SLOT_SPOWER_DONE		0x00000702
+#define FIRENZE_PCI_SLOT_NORMAL			PCI_SLOT_STATE_NORMAL
+#define FIRENZE_PCI_SLOT_LINK			PCI_SLOT_STATE_LINK
+#define   FIRENZE_PCI_SLOT_LINK_START		(FIRENZE_PCI_SLOT_LINK + 1)
+#define FIRENZE_PCI_SLOT_HRESET			PCI_SLOT_STATE_HRESET
+#define   FIRENZE_PCI_SLOT_HRESET_START		(FIRENZE_PCI_SLOT_HRESET + 1)
+#define FIRENZE_PCI_SLOT_FRESET			PCI_SLOT_STATE_FRESET
+#define   FIRENZE_PCI_SLOT_FRESET_START		(FIRENZE_PCI_SLOT_FRESET + 1)
+#define   FIRENZE_PCI_SLOT_FRESET_WAIT_RSP	(FIRENZE_PCI_SLOT_FRESET + 2)
+#define   FIRENZE_PCI_SLOT_FRESET_DELAY		(FIRENZE_PCI_SLOT_FRESET + 3)
+#define   FIRENZE_PCI_SLOT_FRESET_POWER_STATE	(FIRENZE_PCI_SLOT_FRESET + 4)
+#define   FIRENZE_PCI_SLOT_FRESET_POWER_OFF	(FIRENZE_PCI_SLOT_FRESET + 5)
+#define   FIRENZE_PCI_SLOT_FRESET_POWER_ON	(FIRENZE_PCI_SLOT_FRESET + 6)
+#define   FIRENZE_PCI_SLOT_PERST_DEASSERT	(FIRENZE_PCI_SLOT_FRESET + 7)
+#define   FIRENZE_PCI_SLOT_PERST_DELAY		(FIRENZE_PCI_SLOT_FRESET + 8)
+#define FIRENZE_PCI_SLOT_PFRESET		PCI_SLOT_STATE_PFRESET
+#define   FIRENZE_PCI_SLOT_PFRESET_START	(FIRENZE_PCI_SLOT_PFRESET + 1)
+#define FIRENZE_PCI_SLOT_GPOWER			PCI_SLOT_STATE_GPOWER
+#define   FIRENZE_PCI_SLOT_GPOWER_START		(FIRENZE_PCI_SLOT_GPOWER + 1)
+#define FIRENZE_PCI_SLOT_SPOWER			PCI_SLOT_STATE_SPOWER
+#define   FIRENZE_PCI_SLOT_SPOWER_START		(FIRENZE_PCI_SLOT_SPOWER + 1)
+#define   FIRENZE_PCI_SLOT_SPOWER_DONE		(FIRENZE_PCI_SLOT_SPOWER + 2)
 
 /* Timeout for power status */
 #define FIRENZE_PCI_SLOT_RETRIES	500