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authorBenjamin Herrenschmidt <benh@kernel.crashing.org>2015-06-18 15:30:33 +1000
committerStewart Smith <stewart@linux.vnet.ibm.com>2015-06-18 16:11:34 +1000
commit451530398b744ebe0401abecfc0315b4b8ce99c2 (patch)
treeb6e8242fbbeea867b140c45f872a6f421ecb79ee
parent092d2a8e58cad4c9cac3dc573f5af6409d2d1ce6 (diff)
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Set proper value for RPR registerskiboot-5.0.4
The value was provided by Dave Larson and is what pHyp uses Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
-rw-r--r--asm/head.S3
-rw-r--r--include/processor.h1
2 files changed, 4 insertions, 0 deletions
diff --git a/asm/head.S b/asm/head.S
index 0b90d22..75a70a0 100644
--- a/asm/head.S
+++ b/asm/head.S
@@ -703,6 +703,9 @@ init_shared_sprs:
sync
mtspr SPR_HMEER,%r3
isync
+ /* RPR (per-LPAR but let's treat it as replicated for now) */
+ LOAD_IMM64(%r3,0x00000103070F1F3F)
+ mtspr SPR_RPR,%r3
9: blr
.global init_replicated_sprs
diff --git a/include/processor.h b/include/processor.h
index cdc5919..143308e 100644
--- a/include/processor.h
+++ b/include/processor.h
@@ -52,6 +52,7 @@
#define SPR_SRR0 0x01a /* RW: Exception save/restore reg 0 */
#define SPR_SRR1 0x01b /* RW: Exception save/restore reg 1 */
#define SPR_CFAR 0x01c /* RW: Come From Address Register */
+#define SPR_RPR 0x0ba /* RW: Relative Priority Register */
#define SPR_TBRL 0x10c /* RO: Timebase low */
#define SPR_TBRU 0x10d /* RO: Timebase high */
#define SPR_SPRC 0x114 /* RW: Access to uArch SPRs (ex SCOMC) */