Move around comment in interrupts.h

Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>

1 files changed, 32 insertions, 33 deletions

diff --git a/include/interrupts.h b/include/interrupts.h
index 19f542f..daa9747 100644
--- a/include/interrupts.h
+++ b/include/interrupts.h
@@ -181,38 +181,6 @@
  *
  */
 
-/* Note about interrupt numbers on P9
- * ==================================
- *
- * P9 uses a completely different interrupt controller, XIVE.
- *
- * It targets objects using a combination of block number and
- * index within a block. However, we try to avoid exposing that
- * split to the OS in order to keep some abstraction in case the
- * way we allocate these change.
- *
- * The lowest level entity in Xive is the EST (state bit array).
- *
- * Those are spread between PHBs, PSI bridge and XIVE itself which
- * provide a large amount of state bits for IPIs and other SW and HW
- * generated interrupts by sources that don't have their own ESB logic
- *
- * Due to that spread, they aren't a good representation of a global
- * interrupt number.
- *
- * Each such source however needs to be targetted at an EAS (IVT)
- * entry in a table which will control targetting information and
- * associate that interrupt with a logical number.
- *
- * Thus that table entry number represents a good "global interrupt
- * number". Additionally, for the host OS, we will keep the logical
- * number equal to the global number.
- *
- * The details of how these are assigned on P9 can be found in
- * hw/xive.c. P9 HW will generally not use the definitions and
- * functions in this file (or the corresponding core/interrupts.c).
- */
-
 uint32_t p8_chip_irq_block_base(uint32_t chip, uint32_t block);
 uint32_t p8_chip_irq_phb_base(uint32_t chip, uint32_t phb);
 uint32_t p8_irq_to_chip(uint32_t irq);
@@ -249,12 +217,43 @@ uint32_t p8_irq_to_phb(uint32_t irq);
 #define P8_IRQ_PSI_LOCAL_COUNT		5
 #define P8_IRQ_PSI_ALL_COUNT		6
 
+/* TBD: NX, AS, ...
+ */
 /* These are passed onto Linux */
 #define P8_IRQ_PSI_LINUX_BASE		5
 #define P8_IRQ_PSI_HOST_ERR		5	/* Used for UART */
 #define P8_IRQ_PSI_LINUX_COUNT		1
 
-/* TBD: NX, AS, ...
+/* Note about interrupt numbers on P9
+ * ==================================
+ *
+ * P9 uses a completely different interrupt controller, XIVE.
+ *
+ * It targets objects using a combination of block number and
+ * index within a block. However, we try to avoid exposing that
+ * split to the OS in order to keep some abstraction in case the
+ * way we allocate these change.
+ *
+ * The lowest level entity in Xive is the ESB (state bits).
+ *
+ * Those are spread between PHBs, PSI bridge and XIVE itself which
+ * provide a large amount of state bits for IPIs and other SW and HW
+ * generated interrupts by sources that don't have their own ESB logic
+ *
+ * Due to that spread, they aren't a good representation of a global
+ * interrupt number.
+ *
+ * Each such source however needs to be targetted at an EAS (IVT)
+ * entry in a table which will control targetting information and
+ * associate that interrupt with a logical number.
+ *
+ * Thus that table entry number represents a good "global interrupt
+ * number". Additionally, for the host OS, we will keep the logical
+ * number equal to the global number.
+ *
+ * The details of how these are assigned on P9 can be found in
+ * hw/xive.c. P9 HW will only use a subset of the definitions and
+ * functions in this file (or the corresponding core/interrupts.c).
  */
 
 /*