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| author | Oliver O'Halloran <oohall@gmail.com> | 2017-05-04 15:47:04 +1000 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2017-08-18 13:30:38 +1000 |
| commit | 81dfc40b766994a7d3235dfcb845ca94f3ebc12e (patch) | |
| tree | 0f6b11e8874fdf50f477ea78d0061e68f2a1051c | |
| parent | dac21e8d83b485c7d376b78bcb762d63261defcf (diff) | |
| download | skiboot-81dfc40b766994a7d3235dfcb845ca94f3ebc12e.zip skiboot-81dfc40b766994a7d3235dfcb845ca94f3ebc12e.tar.gz skiboot-81dfc40b766994a7d3235dfcb845ca94f3ebc12e.tar.bz2 | |
head.S: store all of LR and CTR
When saving the CTR and LR registers the skiboot exception handlers use the
'stw' instruction which only saves the lower 32 bits of the register. Given
these are both 64 bit registers this leads to some strange register dumps,
for example:
***********************************************
Unexpected exception 200 !
SRR0 : 0000000030016968 SRR1 : 9000000000201000
HSRR0: 0000000000000180 HSRR1: 9000000000001000
LR : 3003438830823f50 CTR : 3003438800000018
CFAR : 00000000300168fc
CR : 40004208 XER: 00000000
In this dump the upper 32 bits of LR and CTR are actually stack gunk
which obscures the underlying issue.
Signed-off-by: Oliver O'Halloran <oohall@gmail.com>
Acked-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
(cherry picked from commit 70bc370883330c8b1076555c126647a3cdf88706)
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | asm/head.S | 4 |
1 files changed, 2 insertions, 2 deletions
@@ -191,8 +191,8 @@ _exception: mflr %r6 stw %r3,STACK_CR(%r1) stw %r4,STACK_XER(%r1) - stw %r5,STACK_CTR(%r1) - stw %r5,STACK_LR(%r1) + std %r5,STACK_CTR(%r1) + std %r5,STACK_LR(%r1) mfspr %r3,SPR_SRR0 mfspr %r4,SPR_SRR1 mfspr %r5,SPR_HSRR0 |