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| author | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-11-11 17:02:59 +1100 |
|---|---|---|
| committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2016-01-21 15:25:08 +1100 |
| commit | 6a9c0af912574a8d5f298d8f1c3a4ff8d8b753a2 (patch) | |
| tree | d460ac43af54d96bc1f0576a5454dffd9ece3a42 | |
| parent | 35451e78e897e68cfc72a69ea5e34afb334b048e (diff) | |
| download | skiboot-6a9c0af912574a8d5f298d8f1c3a4ff8d8b753a2.zip skiboot-6a9c0af912574a8d5f298d8f1c3a4ff8d8b753a2.tar.gz skiboot-6a9c0af912574a8d5f298d8f1c3a4ff8d8b753a2.tar.bz2 | |
Fix endian flip in printf for FSP in hdata/fsp.c
commit dfab2fb87c2d83e240a002e8829b525d10342df3 upstream
Harmless for skiboot as we're BE.
When building and running unit tests on LE though, we got an incorrect
hw/software version for FSP hardware/software for hdata_to_dt test.
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
| -rw-r--r-- | hdata/fsp.c | 5 | ||||
| -rw-r--r-- | hdata/test/p81-811.spira.dt | 2 |
2 files changed, 4 insertions, 3 deletions
diff --git a/hdata/fsp.c b/hdata/fsp.c index 595e1f8..158b78b 100644 --- a/hdata/fsp.c +++ b/hdata/fsp.c @@ -39,8 +39,9 @@ static struct dt_node *fsp_create_node(const void *spss, int i, } prlog(PR_INFO, "FSP #%d: FSP HW version %d, SW version %d," - " chip DD%d.%d\n", - i, sp_impl->hw_version, sp_impl->sw_version, + " chip DD%d.%d\n", i, + be16_to_cpu(sp_impl->hw_version), + be16_to_cpu(sp_impl->sw_version), sp_impl->chip_version >> 4, sp_impl->chip_version & 0xf); mask = SPSS_SP_IMPL_FLAGS_INSTALLED | SPSS_SP_IMPL_FLAGS_FUNCTIONAL; if ((be16_to_cpu(sp_impl->func_flags) & mask) != mask) { diff --git a/hdata/test/p81-811.spira.dt b/hdata/test/p81-811.spira.dt index 388bb56..025779a 100644 --- a/hdata/test/p81-811.spira.dt +++ b/hdata/test/p81-811.spira.dt @@ -70,7 +70,7 @@ XSCOM: Found HW ID 0x10 (PCID 0x2) @ 0x3c8000000000 VPD: CCIN desc not available for : 54E8 XSCOM: Found HW ID 0x11 (PCID 0x3) @ 0x3c8800000000 VPD: CCIN desc not available for : 54E8 -FSP #0: FSP HW version 512, SW version 256, chip DD1.0 +FSP #0: FSP HW version 2, SW version 1, chip DD1.0 CEC: HUB FRU 0 is CPU Card CEC: 2 chips in FRU CEC: Murano ! |