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author | Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com> | 2015-03-11 16:02:18 +0530 |
---|---|---|
committer | Stewart Smith <stewart@linux.vnet.ibm.com> | 2015-03-26 11:12:18 +1100 |
commit | a2f6ec1ec030f9f038615f889a75376c4db99d91 (patch) | |
tree | f9288f6ed358cb9521b54c3cf72778b0875d238f | |
parent | fcca42f63e16aa186e3ef1bb088fb5abfef3590e (diff) | |
download | skiboot-a2f6ec1ec030f9f038615f889a75376c4db99d91.zip skiboot-a2f6ec1ec030f9f038615f889a75376c4db99d91.tar.gz skiboot-a2f6ec1ec030f9f038615f889a75376c4db99d91.tar.bz2 |
opal: Recover from TFMR DEC parity error.
Recovery process for TFMR DEC parity error:
- Set DEC Register with all ones.
- Reset TFMR DEC parity error bit.
To inject TFMR DEC parity error issue:
$ putscom pu.ex 10013281 0006080000000000 -all
Signed-off-by: Mahesh Salgaonkar <mahesh@linux.vnet.ibm.com>
Signed-off-by: Stewart Smith <stewart@linux.vnet.ibm.com>
-rw-r--r-- | hw/chiptod.c | 11 | ||||
-rw-r--r-- | include/processor.h | 1 |
2 files changed, 11 insertions, 1 deletions
diff --git a/hw/chiptod.c b/hw/chiptod.c index 6f6800f..1c77cb7 100644 --- a/hw/chiptod.c +++ b/hw/chiptod.c @@ -697,6 +697,14 @@ static bool tfmr_recover_non_tb_errors(uint64_t tfmr) tfmr_reset_errors |= SPR_TFMR_HDEC_PARITY_ERROR; } + if (tfmr & SPR_TFMR_DEC_PARITY_ERR) { + /* Set DEC with all ones */ + mtspr(SPR_DEC, ~0); + + /* set bit 59 to clear TFMR DEC parity error. */ + tfmr_reset_errors |= SPR_TFMR_DEC_PARITY_ERR; + } + /* Write TFMR twice to clear the error */ mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors); mtspr(SPR_TFMR, base_tfmr | tfmr_reset_errors); @@ -848,7 +856,8 @@ int chiptod_recover_tb_errors(void) /* * Now that TB is running, check for TFMR non-TB errors. */ - if (tfmr & SPR_TFMR_HDEC_PARITY_ERROR) { + if ((tfmr & SPR_TFMR_HDEC_PARITY_ERROR) || + (tfmr & SPR_TFMR_DEC_PARITY_ERR)) { if (!tfmr_recover_non_tb_errors(tfmr)) { rc = 0; goto error_out; diff --git a/include/processor.h b/include/processor.h index 9140564..30527b1 100644 --- a/include/processor.h +++ b/include/processor.h @@ -47,6 +47,7 @@ /* SPR register definitions */ #define SPR_DSISR 0x012 /* RW: Data storage interrupt status reg */ #define SPR_DAR 0x013 /* RW: Data address reg */ +#define SPR_DEC 0x016 /* RW: Decrement Register */ #define SPR_SDR1 0x019 #define SPR_SRR0 0x01a /* RW: Exception save/restore reg 0 */ #define SPR_SRR1 0x01b /* RW: Exception save/restore reg 1 */ |