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| author | Ryan Grimm <grimm@linux.vnet.ibm.com> | 2014-11-14 15:21:27 -0500 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2014-11-17 10:21:39 +1100 |
| commit | 7be569c98344943fd95daf0618993bb58e58209c (patch) | |
| tree | 9b401c2840abaa524e84208a816881fb91622af7 | |
| parent | d5a261b3aa266ff8a780b66569175aef96d0a95a (diff) | |
| download | skiboot-7be569c98344943fd95daf0618993bb58e58209c.zip skiboot-7be569c98344943fd95daf0618993bb58e58209c.tar.gz skiboot-7be569c98344943fd95daf0618993bb58e58209c.tar.bz2 | |
PHB3: wait 1s after PERST deassert for CAPP adapters
On a re-ipl or warm reboot, Sapphire asserts and deasserts PERST to each slot.
This results in the fpga image loaded into the flash for a CAPP adapter. HMIs
have been observed with a 200ms wait following PERST deassert, so bump time up
to 1s. Do this for all cases because re-ipl does not preserve memory and we'd
need a mechanism for Sapphire know that there is a CAPP adapter.
We might be able to reduce this to 750ms or 500ms but need more testing. Use
1s to be safe. Also, phyp fw uses 1s after deassert.
Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| -rw-r--r-- | hw/phb3.c | 5 |
1 files changed, 1 insertions, 4 deletions
@@ -2127,10 +2127,7 @@ static int64_t phb3_sm_fundamental_reset(struct phb3 *p) p->state = PHB3_STATE_FRESET_DEASSERT_DELAY; /* CAPP fpga requires 1s to flash before polling link */ - if (p->flags & PHB3_CAPP_RECOVERY) - return phb3_set_sm_timeout(p, secs_to_tb(1)); - /* Wait 200ms before polling link dd*/ - return phb3_set_sm_timeout(p, msecs_to_tb(200)); + return phb3_set_sm_timeout(p, secs_to_tb(1)); case PHB3_STATE_FRESET_DEASSERT_DELAY: /* Switch to generic link poll state machine */ |