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| author | Ryan Grimm <grimm@linux.vnet.ibm.com> | 2014-09-29 18:48:15 -0400 |
|---|---|---|
| committer | Benjamin Herrenschmidt <benh@kernel.crashing.org> | 2014-09-30 14:45:39 +1000 |
| commit | 8b925076b139a973b25ef88d3d701a810b38f1c0 (patch) | |
| tree | 46c81f61f1f4bdeab8f26dc30c041acf74c1d668 | |
| parent | 32765e19a22f8366e562d7649cd726dc415600e1 (diff) | |
| download | skiboot-8b925076b139a973b25ef88d3d701a810b38f1c0.zip skiboot-8b925076b139a973b25ef88d3d701a810b38f1c0.tar.gz skiboot-8b925076b139a973b25ef88d3d701a810b38f1c0.tar.bz2 | |
phb3/capi: Initialize capp regs with field values.
FLUSH_SUE_STATE_MAP change fixes a problem with recovery. We were using an old
lab value that marked PTE entries in a shared state. After recovery, PTE
entries were getting flushed out to memory with an SUE, resulting in a machine
check. The new value means PTE entries are dropped on recovery.
For, APC_MASTER_PB_CTRL spec says to use initfile value and bit 3 should be
set. Initfile missing bit 3 so do a RMW. Bit 3 enables CAPP combined
response.
CAPP_EPOCH_TIMER_CTRL enables epoch timers and the recovery timer when recovery
is enabled. Also relax epoch timer period mask due to a bug.
TRANSPORT_CONTROL reg set bit 37 - rfs_benign_ptr_data in addition to spec
value. Should be set in initifile in future.
Rename APC_MASTER_CONFIG to APC_MASTER_CAPI_CTRL to match workbook name.
Signed-off-by: Ryan Grimm <grimm@linux.vnet.ibm.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
| -rw-r--r-- | hw/phb3.c | 16 | ||||
| -rw-r--r-- | include/capp.h | 2 |
2 files changed, 10 insertions, 8 deletions
@@ -2871,18 +2871,20 @@ static int64_t capp_load_ucode(struct phb3 *p) static void phb3_init_capp_regs(struct phb3 *p) { - /* writing these vals directly based on lab procedures - but some values included in microcode need to investigate */ + /* writing field vals directly */ + uint64_t reg; + xscom_read(p->chip_id, APC_MASTER_PB_CTRL, ®); + reg |= PPC_BIT(3); + xscom_write(p->chip_id, APC_MASTER_PB_CTRL, reg); /* port0 port1 * 100 PHB0 disabled * we're told it's the same for Venice */ - xscom_write(p->chip_id, APC_MASTER_PB_CTRL, 0x10000000000000FF); - xscom_write(p->chip_id, APC_MASTER_CONFIG, 0x4070000000000000); + xscom_write(p->chip_id, APC_MASTER_CAPI_CTRL, 0x4070000000000000); /* tlb and mmio */ - xscom_write(p->chip_id, TRANSPORT_CONTROL, 0x4028000100000000); + xscom_write(p->chip_id, TRANSPORT_CONTROL, 0x4028000104000000); xscom_write(p->chip_id, CANNED_PRESP_MAP0, 0); xscom_write(p->chip_id, CANNED_PRESP_MAP1, 0xFFFFFFFF00000000); @@ -2891,8 +2893,8 @@ static void phb3_init_capp_regs(struct phb3 *p) /* error recovery */ xscom_write(p->chip_id, CAPP_ERR_STATUS_CTRL, 0); - xscom_write(p->chip_id, FLUSH_SUE_STATE_MAP, 0x0ABCDEF000000000); - xscom_write(p->chip_id, CAPP_EPOCH_TIMER_CTRL, 0x00000000FFF8FFE0); + xscom_write(p->chip_id, FLUSH_SUE_STATE_MAP, 0x1DC20B6600000000); + xscom_write(p->chip_id, CAPP_EPOCH_TIMER_CTRL, 0xC0000000FFF0FFE0); xscom_write(p->chip_id, FLUSH_UOP_CONFIG1, 0xB188280728000000); xscom_write(p->chip_id, FLUSH_UOP_CONFIG2, 0xB188400F00000000); xscom_write(p->chip_id, SNOOP_CAPI_CONFIG, 0xA1F0000000000000); diff --git a/include/capp.h b/include/capp.h index 417e952..c0b67e1 100644 --- a/include/capp.h +++ b/include/capp.h @@ -58,7 +58,7 @@ enum capp_reg { #define CAPP_APC_MASTER_ARRAY_WRITE_REG 0x2013802 #define APC_MASTER_PB_CTRL 0x2013018 -#define APC_MASTER_CONFIG 0x2013019 +#define APC_MASTER_CAPI_CTRL 0x2013019 #define TRANSPORT_CONTROL 0x201301C #define CANNED_PRESP_MAP0 0x201301D #define CANNED_PRESP_MAP1 0x201301E |