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author | Stewart Smith <stewart@linux.ibm.com> | 2019-05-31 16:13:12 +1000 |
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committer | Stewart Smith <stewart@linux.ibm.com> | 2019-06-03 10:20:00 +1000 |
commit | 8ab9f9d33f0c68839add6c8af750e1a47abfcb92 (patch) | |
tree | 65ee4b73d87c79078ed09dc515f85736801c72bb | |
parent | e6d95f28f325cb4e387f6bc88096ba8e73665af5 (diff) | |
download | skiboot-8ab9f9d33f0c68839add6c8af750e1a47abfcb92.zip skiboot-8ab9f9d33f0c68839add6c8af750e1a47abfcb92.tar.gz skiboot-8ab9f9d33f0c68839add6c8af750e1a47abfcb92.tar.bz2 |
doc: prettify OPAL_PCI_SET_PHB_MEM_WINDOW
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
-rw-r--r-- | doc/opal-api/opal-pci-set-phb-mem-window-28.rst | 23 |
1 files changed, 15 insertions, 8 deletions
diff --git a/doc/opal-api/opal-pci-set-phb-mem-window-28.rst b/doc/opal-api/opal-pci-set-phb-mem-window-28.rst index 0dc6b70..e23d841 100644 --- a/doc/opal-api/opal-pci-set-phb-mem-window-28.rst +++ b/doc/opal-api/opal-pci-set-phb-mem-window-28.rst @@ -1,15 +1,20 @@ +.. _OPAL_PCI_SET_PHB_MEM_WINDOW: + OPAL_PCI_SET_PHB_MEM_WINDOW =========================== -:: + +.. code-block:: c #define OPAL_PCI_SET_PHB_MEM_WINDOW 28 - static int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, - uint16_t window_type, - uint16_t window_num, - uint64_t addr, - uint64_t pci_addr, - uint64_t size) + int64_t opal_pci_set_phb_mem_window(uint64_t phb_id, + uint16_t window_type, + uint16_t window_num, + uint64_t addr, + uint64_t pci_addr, + uint64_t size); + +.. note:: Appears to be POWER7 p7ioc specific. Likely to be removed soon. **WARNING:** following documentation is from old sources, and is possibly not representative of OPALv3 as implemented by skiboot. This should be @@ -71,7 +76,9 @@ segment_size times the number of segments within this MMIO window. The host must set PHB memory windows to be within the system real address ranges indicated in the PHB parent HDT hub node ibm,opal-mmio-real property. -Return value: :: +Return value: + +.. code-block:: c if (!phb) return OPAL_PARAMETER; |