aboutsummaryrefslogtreecommitdiff
path: root/src
AgeCommit message (Collapse)AuthorFilesLines
2023-10-30parisc: Detect Astro Runway port and CPUsdevel64Helge Deller3-24/+134
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-30parisc/sti: Fix STI crash with fonts with 64-bit Linux kernelHelge Deller1-0/+45
Just swapping font "next-font" pointers breaks the sti driver on older 64-bit Linux kernels which take the "next_font" pointer as unsigned int (instead of signed int) and thus calculates a wrong font start address. Avoid the crash by sorting the fonts in the STI ROM before the OS starts. A Linux kernel patch to avoid the crash was added in kernel 6.7. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-29parisc: Add Astro/Elroy constants for debuggingHelge Deller3-15/+29
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-29parisc: Add subfunction 2 for PDC_MODEL_VERSIONSHelge Deller1-0/+5
Is asked by ODE on C3700. Apparently PDC PAT version. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-29parisc: Don't enable PSW.W at pdc exitHelge Deller1-2/+2
This fixes ODE for C3700, which aparently tried to run with PSW.W=1 and failed. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-29parisc: Lock 64-bit PDC calls until PDC_MODEL/PDC_MODEL_CAPABILITIES callHelge Deller1-2/+16
The OS needs to "unlock" the 64-bit functions. This fixes the ODE tool to detect the mapper instead of mapper2 tool. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-29parisc: Use correct CPU and FPU model numbersHelge Deller2-11/+13
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-28parisc: Fix boot path & PDC versionHelge Deller1-7/+9
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-28parisc: Add PDC_PAT_CPU functionHelge Deller1-2/+39
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-28parisc: Fix ODE on B160LHelge Deller3-34/+88
Fully implement device tree Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-28parisc: Add timer2() wait function to cope with 32-bit timer limitHelge Deller4-7/+54
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-28parisc: More USB OHCI fixesHelge Deller4-18/+21
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-27parisc: Fix graphics output to LASI artist card on PA2.0 machinesHelge Deller3-15/+12
This fixes the graphics output, but keyboard is still on serial only. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-27parisc: Provide MEM_PDC_ENTRY as PDC entry point on SMP rendezvousHelge Deller3-5/+6
Hand over the architected MEM_PDC_ENTRY address (0x4800) instead of the native address of pdc_entry() when providing the PDC entry point in the SMP rendezvous function. This fixes the 64-bit SMP boot, since it avoids the ldil instruction which trashes he upper 32-bits. Secondly, the linux kernel checks the provided value against the PAGE0->mem_pdc value and complains if the differ. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-23parisc: Use new default sw_id for the machinesHelge Deller3-9/+11
2004000160 for the B160L, and 2004003700 for the C3700. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Hackish fix to save PSW.W across pdc/iodc callHelge Deller1-4/+8
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Add PSW.W handling in iodc_entryHelge Deller1-1/+16
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: We only support a 32-bit PDC for now.Helge Deller1-2/+2
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Fix return value of PDC_CACHE_RET_SPID space-id bitsHelge Deller1-3/+2
If SR-hasing is disabled, we need to return zero. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Implement PDC_PAT_PD_GET_ADDR_MAPHelge Deller2-2/+18
Implemented for memory only for now... Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: initialize result of pdc_model call prior returnHelge Deller1-0/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Add default PSW bit setting to pdc_model structHelge Deller2-1/+6
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Store user-specified sw_id in pdc_model fieldHelge Deller1-0/+2
If user gives a sw_id, use it for all emulated CPUs. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Add initial PDC_PAT_CELL and PDC_PAT_CHASSIS_LOG callsHelge Deller1-5/+46
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Add pdcpat.h for PDC PAT functionsHelge Deller3-3/+395
A minimal set of PDC PAT (PARISC-on-TAHOE, aka 64-bit PDC calls) is needed to support booting a 64-bit PARISC kernel. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Do not allow 64-bit PDC calls (yet)Helge Deller1-2/+2
Need to implement 64-bit register save/restore before enabling this option. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-22parisc: Save and restore current PSW_W across PDC callHelge Deller2-5/+19
When called from a 64-bit kernel, pdc_psw may be called with PSW.W set, so save and restore it during the call. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-21parisc: Update to version 11Helge Deller1-2/+2
2023-10-17parisc: Better power off message from power buttonHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-17parisc: Fully implement PDC_PSW for 64-bit CPUsHelge Deller2-4/+18
PDC_PSW tells the hardware how the default PSW is implemented. The w field indicates the default width of the processor. The w field also determines whether the External Interrupt Request (EIR) register is treated as a right-justified 32-bit register or a full 64-bit register. The e field indicates the default endianness of the processor. Both bits determine how the PSW W-bit and E-bit will be set on an interruption. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-17parisc: Fix mfctl,w instruction and thus 64-bit detectionHelge Deller1-2/+3
Use the wide version of mfctl to read the %sar register. Only the w-version is able to detect if we run on a 64-bit CPU. Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc: SEABIOS_HPPA_VERSION 10seabios-hppa-v10devel5Helge Deller1-2/+2
Enhancements: - Initial support for 64-bit CPUs with Astro/Elroy (e.g. C3700 workstation) - USB support (OHCI) - better PCI support - esp-scsi fixes from Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/c3700: Add support for C3700 workstation with Astro/ElroyHelge Deller14-261/+1339
Major changes to support 64-bit machines with Astro and Elroy chips. This patch adds support for the C3700 workstation. Changes include: - Detect if the emulated CPU runs as 32-bit PA1.x or 64-bit PA2.x CPU - Add support for Astro and Elroy chips: * build interrupt routing table (IRT) * add PCI irq to pci_device struct - Enhance PCI bus scanning * Add support for various PCI cards (serial, USB, graphics, ...) - Change PCI I/O accessor functions: * readX()/writeX() do byteswapping and take an ioremapped address * __raw_readX()/__raw_writeX() don't byteswap and take an ioremapped address. * gsc_*() don't byteswap and operate on physical addresses Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/malloc: Drop debug outputHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/blockcmd: Drop debug outputHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/kbd: Drop debug outputHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/usb: Fix usb host for big-endian machines (like parisc)Helge Deller2-51/+54
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/serialio: Use portaddr_t type for DebugOutputPortHelge Deller1-1/+2
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/rtc: Drop parisc specific RTC portsHelge Deller1-7/+0
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/ata: Drop parisc specific ISA ATA portsHelge Deller1-8/+0
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/block: Disable debug lineHelge Deller1-1/+1
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/timer: Drop PAGE0 from timer fileHelge Deller1-2/+0
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc: Add PDC_CACHE_RET_SPID functionHelge Deller1-0/+5
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc/pdc.h: Add some additional PDC constantsHelge Deller1-2/+25
Signed-off-by: Helge Deller <deller@gmx.de>
2023-10-14parisc: Fix serial output at early bootupHelge Deller1-3/+11
If some bug happens during early bootup, the mem_cons might not have been initialized yet. In that case use default PARISC_SERIAL_CONSOLE to show something. Signed-off-by: Helge Deller <deller@gmx.de>
2023-09-16esp-scsi: handle non-DMA SCSI commands with no data phaseMark Cave-Ayland1-1/+10
The existing esp-scsi state machine checks for the STAT_TC bit to exit state 1 but in the case where there is no data phase, a non-DMA command is executed which doesn't set STAT_TC. This only works because QEMU currently always sets STAT_TC just after issuing every SCSI command. Update the esp-scsi state machine so that in the case where there is no data phase, we immediately execute CMD_ICCS instead of waiting for STAT_TC to be set which will never happen with a non-DMA CMD_SELATN command. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Message-ID: <20230807065300.366070-4-mark.cave-ayland@ilande.co.uk> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-09-16esp-scsi: check for INTR_BS/INTR_FC instead of STAT_TC for command completionMark Cave-Ayland1-14/+22
The ESP SELATN command used to send SCSI commands from the ESP to the SCSI bus is not a DMA command and therefore does not affect the STAT_TC bit. The only reason this works at all is due to a bug in QEMU which (currently) always updates the STAT_TC bit in ESP_RSTAT regardless of the state of the ESP_CMD_DMA bit. According to the NCR datasheet [1] the INTR_BS/INTR_FC bits are set when the SELATN command has completed, so update the existing logic to check for these bits in ESP_RINTR instead. Note that the read of ESP_RINTR needs to be restricted to state == 0 as reading ESP_RINTR resets the ESP_RSTAT register which breaks the STAT_TC check when state == 1. This commit also includes an extra read of ESP_INTR to clear all the interrupt bits before submitting the SELATN command to ensure that we don't accidentally immediately progress to the data phase handling logic where ESP_RINTR bits have already been set by a previous ESP command. [1] "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller" NCR_53C94_53C95_53C96_Data_Sheet_Feb90.pdf Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Message-ID: <20230807065300.366070-3-mark.cave-ayland@ilande.co.uk> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-09-16esp-scsi: flush FIFO before sending SCSI commandMark Cave-Ayland1-0/+4
The ESP FIFO is used as a buffer for DMA requests and so isn't guaranteed to be empty in the case of SCSI errors or a mixed DMA/non-DMA request. Flush the FIFO before sending a SCSI command to guarantee that it is correctly positioned at the start of the FIFO. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-ID: <20230807065300.366070-2-mark.cave-ayland@ilande.co.uk> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2023-09-13parisc: SEABIOS_HPPA_VERSION 9seabios-hppa-v9devel-btlb-2Helge Deller1-2/+2
Enhancements: - Support for Block-TLB (BTLB) on 32-bit CPUs Signed-off-by: Helge Deller <deller@gmx.de>
2023-09-13parisc: Implement Block-TLB (BTLB) support for 32-bit CPUsHelge Deller1-20/+11
SeaBIOS has no information about the lower implementation details for Block-TLB (or generic TLB) support, so it simply hands over the parameters in the CPU registers provided by the operating system to the PDC_BLOCK_TLB PDC function to QEMU. Calling QEMU happens via a diagnostics instruction (diag 0x100) which QEMU will respond to. Older QEMU versions without the BTLB support will simply log that they ignored the diag instruction, and SeaBIOS will return PDC_BAD_OPTION for this PDC call in that case. Signed-off-by: Helge Deller <deller@gmx.de>
generated by cgit v1.1 at 2025-09-18 09:31:57 +0000