Age | Commit message (Collapse) | Author | Files | Lines |
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run 64-bit instruction in sr_disable_hash)
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Signed-off-by: Helge Deller <deller@gmx.de>
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Signed-off-by: Helge Deller <deller@gmx.de>
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If some bug happens during early bootup, the mem_cons might
not have been initialized yet. In that case use default
PARISC_SERIAL_CONSOLE to show something.
Signed-off-by: Helge Deller <deller@gmx.de>
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The existing esp-scsi state machine checks for the STAT_TC bit to exit state 1
but in the case where there is no data phase, a non-DMA command is executed
which doesn't set STAT_TC. This only works because QEMU currently always sets
STAT_TC just after issuing every SCSI command.
Update the esp-scsi state machine so that in the case where there is no data
phase, we immediately execute CMD_ICCS instead of waiting for STAT_TC to be
set which will never happen with a non-DMA CMD_SELATN command.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-ID: <20230807065300.366070-4-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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The ESP SELATN command used to send SCSI commands from the ESP to the SCSI bus
is not a DMA command and therefore does not affect the STAT_TC bit. The only
reason this works at all is due to a bug in QEMU which (currently) always
updates the STAT_TC bit in ESP_RSTAT regardless of the state of the ESP_CMD_DMA
bit.
According to the NCR datasheet [1] the INTR_BS/INTR_FC bits are set when the
SELATN command has completed, so update the existing logic to check for these
bits in ESP_RINTR instead. Note that the read of ESP_RINTR needs to be
restricted to state == 0 as reading ESP_RINTR resets the ESP_RSTAT register
which breaks the STAT_TC check when state == 1.
This commit also includes an extra read of ESP_INTR to clear all the interrupt
bits before submitting the SELATN command to ensure that we don't accidentally
immediately progress to the data phase handling logic where ESP_RINTR bits have
already been set by a previous ESP command.
[1] "NCR 53C94, 53C95, 53C96 Advanced SCSI Controller"
NCR_53C94_53C95_53C96_Data_Sheet_Feb90.pdf
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Message-ID: <20230807065300.366070-3-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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The ESP FIFO is used as a buffer for DMA requests and so isn't guaranteed to
be empty in the case of SCSI errors or a mixed DMA/non-DMA request. Flush the
FIFO before sending a SCSI command to guarantee that it is correctly
positioned at the start of the FIFO.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230807065300.366070-2-mark.cave-ayland@ilande.co.uk>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
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Enhancements:
- Support for Block-TLB (BTLB) on 32-bit CPUs
Signed-off-by: Helge Deller <deller@gmx.de>
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SeaBIOS has no information about the lower implementation details for
Block-TLB (or generic TLB) support, so it simply hands over the
parameters in the CPU registers provided by the operating system to the
PDC_BLOCK_TLB PDC function to QEMU.
Calling QEMU happens via a diagnostics instruction (diag 0x100) which
QEMU will respond to. Older QEMU versions without the BTLB support will
simply log that they ignored the diag instruction, and SeaBIOS will
return PDC_BAD_OPTION for this PDC call in that case.
Signed-off-by: Helge Deller <deller@gmx.de>
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Fixes
- boot of HP-UX with SMP, and
- reboot of Linux and HP-UX with SMP
Enhancements:
- show qemu version in boot menu
- adds exit menu entry in boot menu to quit emulation
- allow to trace PCD_CHASSIS codes more specifically
Signed-off-by: Helge Deller <deller@gmx.de>
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Signed-off-by: Helge Deller <deller@gmx.de>
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Qemu currently only supports PSW_Q handling, so enable it by default.
Signed-off-by: Helge Deller <deller@gmx.de>
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