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| author | Gerd Hoffmann <kraxel@redhat.com> | 2020-05-25 11:06:27 +0200 |
|---|---|---|
| committer | Kevin O'Connor <kevin@koconnor.net> | 2020-05-25 11:27:12 -0400 |
| commit | 2e3de6253422112ae43e608661ba94ea6b345694 (patch) | |
| tree | f21d89a69b880902fd19eb95d016886ae0f4afb5 /src/hw | |
| parent | d9aea4a7cd59e00f5ed96b6442806dde0959e1ca (diff) | |
| download | seabios-hppa-2e3de6253422112ae43e608661ba94ea6b345694.zip seabios-hppa-2e3de6253422112ae43e608661ba94ea6b345694.tar.gz seabios-hppa-2e3de6253422112ae43e608661ba94ea6b345694.tar.bz2 | |
pci: fix mmconfig support
The MODESEGMENT condition is backwards, with the effect that
mmconfig mode is not used to configure pci bars during POST.
Oops. Fix it.
The only real mode pci config space access seems to come from the
ipxe option rom initialiation. Which happens to work via mmconfig
because it runs in big real mode so this went unnoticed ...
Fixes: 6a3b59ab9c7d ("pci: add mmconfig support")
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Diffstat (limited to 'src/hw')
| -rw-r--r-- | src/hw/pci.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/hw/pci.c b/src/hw/pci.c index d9dbf31..3df1dae 100644 --- a/src/hw/pci.c +++ b/src/hw/pci.c @@ -28,7 +28,7 @@ static u32 ioconfig_cmd(u16 bdf, u32 addr) void pci_config_writel(u16 bdf, u32 addr, u32 val) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { writel(mmconfig_addr(bdf, addr), val); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -38,7 +38,7 @@ void pci_config_writel(u16 bdf, u32 addr, u32 val) void pci_config_writew(u16 bdf, u32 addr, u16 val) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { writew(mmconfig_addr(bdf, addr), val); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -48,7 +48,7 @@ void pci_config_writew(u16 bdf, u32 addr, u16 val) void pci_config_writeb(u16 bdf, u32 addr, u8 val) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { writeb(mmconfig_addr(bdf, addr), val); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -58,7 +58,7 @@ void pci_config_writeb(u16 bdf, u32 addr, u8 val) u32 pci_config_readl(u16 bdf, u32 addr) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { return readl(mmconfig_addr(bdf, addr)); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -68,7 +68,7 @@ u32 pci_config_readl(u16 bdf, u32 addr) u16 pci_config_readw(u16 bdf, u32 addr) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { return readw(mmconfig_addr(bdf, addr)); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); @@ -78,7 +78,7 @@ u16 pci_config_readw(u16 bdf, u32 addr) u8 pci_config_readb(u16 bdf, u32 addr) { - if (MODESEGMENT && mmconfig) { + if (!MODESEGMENT && mmconfig) { return readb(mmconfig_addr(bdf, addr)); } else { outl(ioconfig_cmd(bdf, addr), PORT_PCI_CMD); |