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authorKevin O'Connor <kevin@koconnor.net>2008-05-24 23:07:16 -0400
committerKevin O'Connor <kevin@koconnor.net>2008-05-24 23:07:16 -0400
commit0f803e460e907c4b8ad5c121ea977d30f87b98dc (patch)
treebd09fc31363f6d1548874e25e62a7c60d61c5355 /src/config.h
parent72743f1d1f19979fcd9c35a0baf3e287091e8eef (diff)
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PCI enhancements.
Allow one to enable/disable PIR tables separately from PCI BIOS support. Use standard PORT_* defs for 0xcf8/0xcfc port accesses. Don't pass PCIDevice pointers around - the struct is small enough to pass in a register. Extract out pci_find_device and pci_find_class functions from PCI BIOS code. Remove PCI_FIXED_HOST_BRIDGE check - the check is too late if standard PCI support isn't available. If standard support is available, then the code should be okay to run.
Diffstat (limited to 'src/config.h')
-rw-r--r--src/config.h4
1 files changed, 4 insertions, 0 deletions
diff --git a/src/config.h b/src/config.h
index 4ae23dc..75f5a7f 100644
--- a/src/config.h
+++ b/src/config.h
@@ -16,6 +16,7 @@
// Configure as a payload coreboot payload.
#define CONFIG_COREBOOT 0
+// Send debugging information to serial port
#define CONFIG_DEBUG_SERIAL 0
#define CONFIG_FLOPPY_SUPPORT 1
@@ -24,6 +25,9 @@
#define CONFIG_KBD_CALL_INT15_4F 1
#define CONFIG_CDROM_BOOT 1
#define CONFIG_CDROM_EMU 1
+// Support built-in PIR table in 0xf000 segment
+#define CONFIG_PIRTABLE 1
+// Support int 1a/b1 PCI BIOS calls
#define CONFIG_PCIBIOS 1
/* define it if the (emulated) hardware supports SMM mode */