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2025-05-20lib: utils: fdt: Claim Zicntr if time CSR emulation is possibleYao Zi1-1/+32
OpenSBI is capable of emulating time CSR through an external timer for HARTs that don't implement a full Zicntr extension. Let's add Zicntr extension in the FDT if CSR emulation is active. This avoids hardcoding the extension in the devicetree, which may confuse pre-SBI bootloaders. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250516133352.36617-4-ziyao@disroot.org Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: sbi: hart: Detect existence of cycle and instret CSRs for ZicntrYao Zi3-8/+39
Zicntr extension specifies three read-only CSRs, time, cycle and instret. It isn't sufficient to report Zicntr is fully supported with only time CSR detected. This patch introduces a bitmap to sbi_hart_features to record availability of these CSRs, which are detected using traps. Zicntr is reported as present if and only if three CSRs are all available on the HARTs. Sites originally depending on SBI_HART_EXT_ZICNTR for detecting existence of time CSR are switched to detect SBI_HART_CSR_TIME instead. Suggested-by: Anup Patel <anup@brainfault.org> Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250516133352.36617-3-ziyao@disroot.org Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils: Fix fdt_mpxy_init() not returning error codeAlvin Chang3-10/+5
It seems that current implementation doesn't fail on fdt_mpxy_init(), because platforms might not have any MPXY devices. In fact, if there are no MPXY devices, fdt_driver_init_all() will return SBI_OK. More importantly, if there is any MPXY device which fails the initialization, OpenSBI must check the error code and stop the booting. Thus, this commit adds the return value for fdt_mpxy_init(). Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250430091007.3768180-1-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mpxy: Remove p2a_db_index from RPMI system MSI attributesAnup Patel2-5/+9
The discovery of P2A doorbell system MSI index is now through RPMI shared memory DT node so remove p2a_db_index from RPMI system MSI attributes and access it as a mailbox channel attribute. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-5-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mailbox: Parse A2P doorbell value from DTAnup Patel1-4/+10
The A2P doorbell value written to the 32-bit A2P doorbell value must be discoverd from device tree instead of always using the default value 1. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-4-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mailbox: Parse P2A doorbell system MSI index from DTAnup Patel2-4/+13
The P2A doorbell system MSI index is expected to be discovered from device tree instead of RPMI system MSI service group attribute. This is based on ARC feedback before RPMI spec was frozen. Let's parse P2A doorbell system MSI index from device tree and also expose it as rpmi channel attribute to RPMI client drivers. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-3-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: utils/mailbox: Update DT register name of A2P doorbellAnup Patel1-2/+2
The latest device tree bindings define A2P doorbell register name as "a2p-doorbell" so update rpmi_shmem_transport_init() accordingly. Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250512083827.804151-2-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-20lib: Emulate AMO instructions when Zaamo is not availableChao-ying Fu6-18/+709
The AMO instructions are very critical for Linux so allow low-end RISC-V implementations without Zaamo to boot Linux by emulating AMO instructions using Zalrsc when OpenSBI is compiled without Zaamo. Signed-off-by: Chao-ying Fu <cfu@mips.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250519121207.976949-1-apatel@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-15Makefile: fix missing .debug_frame DWARF section for GCCParshintsev Anatoly1-0/+1
When OpenSBI is built with a relatively new compiler (gcc-13 and greater) I observed that GDB is unable to produce proper backtraces and some variable values appear corrupted (even if the associated DWARF location descriptor is correct). Turns out that to properly work with debug information, debuggers often need to unwind the stack. They generally rely on Call Frame Information (CFI) records provided by the compiler to facilitate this task. Currently, the GCC compiler offers two mechanisms: - `.debug_frame` section (as described in the DWARF specification). - `.eh_frame` sections (as described in LSB documents). The latter (`.eh_frame`) supports stack unwinding at runtime, providing a framework for C++ exceptions or enabling backtrace generation using libraries like libunwind. However, the downside of this approach is that these sections should be part of loadable segments. The former (`.debug_frame`) is simply an ordinary debug section. Starting from GCC 13, Linux targets enable the `-fasynchronous-unwind-tables` and `-funwind-tables` flags by default. Relevant commit: https://github.com/gcc-mirror/gcc/commit/3cd08f7168 When these flags are active, the compiler generates `.eh_frame` sections instead of `.debug_frame`. Since OpenSBI is built using the **Linux toolchain**, this behavior applies to OpenSBI as well. The problem arises because the SBI build system uses `-Wl,--gc-sections`, which discards the `.eh_frame` section. Possible Fixes: 1. Enforce `.debug_frame` generation – Modify compiler flags to generate `.debug_frame` instead of `.eh_frame`. 2. Preserve `.eh_frame` in the linker script – Add `KEEP(*(.eh_frame))` to ensure the section is not discarded. I chose Option 1 because it avoids any runtime overhead. Signed-off-by: Parshintsev Anatoly <anatoly.parshintsev@syntacore.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250421124729.36364-1-anatoly.parshintsev@syntacore.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-05-15lib: sbi: Use hsm stop for hsm waitNick Hu1-0/+9
If we hotplug a core and then perform a suspend-to-RAM operation on a multi-core platform, the hotplugged CPU may be woken up along with the rest of the system, particularly on platforms that wake all cores from the deepest sleep state. When this happens, the hotplugged CPU enters the sbi_hsm_wait WFI wait loop instead of transitioning into a platform-specific low-power state. To address this, we add a HSM stop call within the wait loop. This allows platforms that support HSM stop to enter a low-power state when the CPU is unexpectedly woken up. Signed-off-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250418064506.15771-1-nick.hu@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi_hart: properly reset SsstateenRadim Krčmář1-3/+12
sstateen* and hstateen* CSRs must be zeroed by M-mode if the mstateen* registers are missing, to avoid security issues. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-10-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi_hart: add Ssstateen extensionRadim Krčmář2-1/+7
We already detect Smstateen, but Ssstateen exists as well and it doesn't have the M-state CSRs. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-9-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi_hart: reset mstateen0Radim Krčmář1-1/+1
The current logic clears some bits based on SBI known extensions. Be safe and do not leave enabled anything that SBI doesn't control. This is not a breaking change, because the register must be initialized to 0 by the ISA on reset, but it is better to not depend on it when we don't need to. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-8-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi_hart: fix sstateen emulationRadim Krčmář1-0/+3
The Sstateen extension defines 4 sstateen registers, but SBI currently configures the execution environment to throw illegal instruction exception when accessing sstateen1-3. SBI should implement all sstateen registers, so delegate the implementation to hardware by setting the SE bit. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-7-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi_hart: reset sstateen and hstateenRadim Krčmář1-0/+6
Not resetting sstateen is a potential security hole, because U might be able to access state that S does not properly context-switch. Similar for hstateen with VS and HS. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-6-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi_hart: reset hstatusRadim Krčmář1-0/+3
hstatus.HU must be cleared, because U-mode could otherwise use the HLS/HSV instructions. This would allow U-mode to read physical memory directly if vgatp and vsatp was 0. The remaining fields don't seem like a security vulnerability now, but clearing the whole CSR is not an issue, so do that be safe. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-5-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi: use 64 bit csr macrosRadim Krčmář2-22/+5
Switch the most obvious cases to new macros. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-4-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-30lib: sbi: add 64 bit csr macrosRadim Krčmář1-0/+20
Most CSRs are XLEN bits wide, but some are 64 bit, so rv32 needs two accesses, plaguing the code with ifdefs. Add new helpers that split 64 bit operation into two operations on rv32. The helpers don't use "csr + 0x10", but append "H" at the end of the csr name to get a compile-time error when accessing a non 64 bit register. This has the downside that you have to use the name when accessing them. e.g. csr_read64(0x1234) or csr_read64(CSR_SATP) won't compile and the error messages you get for these bugs are not straightforward. Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Radim Krčmář <rkrcmar@ventanamicro.com> Link: https://lore.kernel.org/r/20250429142549.3673976-3-rkrcmar@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-24lib: sbi: Set the scratch allocation to alignment to cacheline sizeRaj Vishwanathan5-2/+63
Set the scratch allocation alignment to cacheline size specified by riscv,cbom-block-size in the DTS file to avoid two atomic variables from the same cache line causing livelock on some platforms. If the cacheline is not specified, we set it a default value. Signed-off-by: Raj Vishwanathan <Raj.Vishwanathan@gmail.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250423225045.267983-1-Raj.Vishwanathan@gmail.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23lib: sbi_domain: Reduce memory usage of per-domain hart contextAlvin Chang1-14/+21
In current implementation, the length of hartindex_to_context_table[] array is fixed as SBI_HARTMASK_MAX_BITS. However, the number of harts supported by the platform might not be SBI_HARTMASK_MAX_BITS and is usually smaller than SBI_HARTMASK_MAX_BITS. This means it is unnecessary to allocate such fixed-length array here. Precisely, current implementation always allocates 1024 bytes for hartindex_to_context_table[128] on RV64 platform. However, a platform supports two harts only needs hartindex_to_context_table[2], which only needs 16 bytes. This commit calculates needed size of hartindex_to_context_table[] according to supported number of harts on the platform when registering per-domain data, so that memory usage of per-domain context data can be reduced. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250326062051.3763530-1-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23lib: sbi_platform: Remove the vendor_ext_check hookSamuel Holland2-12/+1
Now that the generic platform only sets .vendor_ext_provider if the function is really implemented, there is no need for a separate hook to check if a vendor extension is implemented. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-11-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23lib: utils/fdt: Remove fdt_match_node()Samuel Holland2-22/+0
This function has been obsoleted by the fdt_driver library and is no longer used. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-10-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Initialize overrides with fdt_driverSamuel Holland1-26/+1
In addition to deduplicating the code, this also improves the match selection logic to respect the priority order of the compatible strings, as implemented in commit 0ffe265fd969 ("lib: utils/fdt: Respect compatible string fallback priority"). Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-9-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Remove platform override hooksSamuel Holland11-116/+16
Now that all of the overrides are modifying generic_platform_ops directly, remove the unused hooks and forwarding functions. The remaining members of struct platform_override match struct fdt_driver, so use that type instead. This allows a future commit to reuse the fdt_driver-based init function. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-8-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Modify platform ops instead of using hooksSamuel Holland12-80/+160
Switch all existing platform overrides to use the helper pattern instead of the platform hooks. After this commit, only the .match_table and .init members of struct platform_override are used. There are two minor behavioral differences: - For Allwinner D1, fdt_add_cpu_idle_states() is now called before the body of generic_final_init(). This should have no functional impact. - For StarFive JH7110, if the /chosen/starfive,boot-hart-id property is missing, the code now falls back to using generic_coldboot_harts, instead of accepting any hart. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-7-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Allow replacing platform operationsSamuel Holland2-20/+38
Currently the generic platform follows the middleware pattern: it implements the sbi_platform hooks, while providing its own set of hooks for further customization. This has a few disadvantages: each location where customization is needed requires a separate platform_override hook, including places where the generic function does nothing except forward to a platform_override hook, and the extra layer of function pointers adds runtime overhead. Let's restructure the generic platform to follow the helper pattern. Allow platform overrides to treat the generic platform as a template, adding or replacing the sbi_platform_operations as needed. Export the generic implementations, so they can be called as helpers from inside the override functions. With this pattern, the platform_override function pointers are replaced by direct calls, and the forwarding functions can be removed. The forwarding functions are not exported, since there is no reason for an override to call them. generic_vendor_ext_check() must be rewritten, since now there is a new way to override vendor_ext_provider. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-6-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: Add an init hook matching fdt_driverSamuel Holland3-7/+14
In preparation for reusing the fdt_driver code to match platform overrides, add a new .init hook matching the type signature from fdt_driver. This hook replaces the existing .fw_init hook, since it is called at roughly the same place in the init process. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-5-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: thead: Avoid casting away constSamuel Holland1-4/+4
struct fdt_match expects match data to be const. Follow this expectation so that no type casting is needed. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-4-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: rzfive: Call andes_pma_setup_regions() only during cold bootSamuel Holland1-2/+10
This function accesses the FDT blob, which means it is only valid to call during cold boot, before a lower privilege level has an opportunity to clobber that memory. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-3-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-23platform: generic: andes: Remove inline definitionsSamuel Holland1-16/+0
The addresses of these functions are used to set function pointers in struct platform_override, so it is not valid for them to be inline. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250325234342.711447-2-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-21lib: sbi_mpxy: Change MPXY state as per-domain dataAlvin Chang1-23/+94
OpenSBI supports multiple supervisor domains run on same platform. When these supervisor domains want to communicate with OpenSBI through MPXY channels, they will allocate MPXY shared memory from their own memory regions. Therefore, the MPXY state data structure must be per-domain and per-hart data structure. This commit registers per-domain MPXY state data in sbi_mpxy_init(). The original MPXY state allocated in scratch region is also removed. We also replace sbi_scratch_thishart_offset_ptr() macro as new sbi_domain_mpxy_state_thishart_ptr() macro which gets MPXY state from per-domain data. Signed-off-by: Alvin Chang <alvinga@andestech.com> Reviewed-by: Yu-Chien Peter Lin <peter.lin@sifive.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250325071314.3113941-1-alvinga@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-21lib: sbi: Handle length of extension name string exceed buffer size errorJimmy Ho1-0/+4
print error message and turncat the string when length of extension name string exceed buffer size Signed-off-by: Jimmy Ho <jimmy.ho@sifive.com> Reviewed-by: Nick Hu <nick.hu@sifive.com> Reviewed-by: Zong Li <zong.li@sifive.com> Link: https://lore.kernel.org/r/20250321001450.11189-1-jimmy.ho@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-15lib: sbi: Remove unnecessary SBI_INIT_LIST_HEADXiang W5-6/+0
No need to initialise the nodes to be added to the linked list Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250319123944.505756-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-15lib: sbi: Simplify structure member offset checkingXiang W4-130/+39
Add a macro assert_member_offset() to perform structure member offset checking. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250319123919.505443-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-15lib: sbi: Fix SHMEM_PHYS_ADDR for RV32Xiang W1-6/+0
Obtaining a 64-bit address under rv32 does not require combining two 32-bit registers because we ignore upper 32-bits on rv32. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250319123832.505033-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-15lib: sbi: Add parameter check in sbi_mpxy_set_shmem()Xiang W1-0/+14
Shared memory needs to be accessed in M-Mode so for now the high address of shared memory can't non-zero. Signed-off-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250319123719.504622-1-wxjstz@126.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-14lib: sbi: Allow programmable counters to monitor cycle/instret events for ↵Leo Yu-Chi Liang1-3/+4
Andes PMU Referencing commit 0c304b661965 ("lib: sbi: Allow programmable counters to monitor cycle/instret events") to support this functionality for Andes PMU. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Link: https://lore.kernel.org/r/20250328084142.540807-1-ycliang@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-14docs: pmu_support: fix example typosLeo Yu-Chi Liang1-2/+2
The (event ID & "second column mask") should equal the "first column match value". Modify the example to fit the description. Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Samuel Holland <samuel.holland@sifive.com> Link: https://lore.kernel.org/r/20250324043943.2513070-1-ycliang@andestech.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-14lib: sbi_ipi: Return error for invalid hartidsAndrew Jones1-0/+9
sbi_send_ipi() should return SBI_ERR_INVALID_PARAM if even one hartid constructed from hart_mask_base and hart_mask, is not valid. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250314163021.154530-6-ajones@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-14sbi: Introduce sbi_hartmask_weightAndrew Jones3-7/+39
Provide a function to count the number of set bits in a hartmask, which builds on a new function for the same that operates on a bitmask. While at it, improve the performance of sbi_popcount() which is used in the implementation. Signed-off-by: Andrew Jones <ajones@ventanamicro.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250314163021.154530-5-ajones@ventanamicro.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-13Makefile: Avoid repeated evaluation of shell commandsSamuel Holland1-6/+8
Recursively expanded variables (defined with '=') are expanded at evaluation time. These version information variables are evaluated inside a recipe as part of GENFLAGS. As a result, the shell commands are executed separately for each compiler invocation. Convert the version information variables to be simply expanded, so the shell commands are executed only once, at Makefile evaluation time. This speeds up the build by as much as 75%. A separate check is needed to maintain the behavior of preferring the value of OPENSBI_BUILD_TIME_STAMP from the environment. Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviewed-by: Xiang W <wxjstz@126.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250313035755.3796610-1-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-13lib: sbi: Enable Control Transfer Records (CTR) Ext using xstateen.Rajnesh Kanwal3-0/+24
The Control Transfer Records (CTR) extension provides a method to record a limited branch history in register-accessible internal chip storage. This extension is similar to Arch LBR in x86 and BRBE in ARM. The Extension has been stable and the latest release can be found here https://github.com/riscv/riscv-control-transfer-records/release Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com> Reviewed-by: Atish Patra <atishp@rivosinc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250307124451.122828-1-rkanwal@rivosinc.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-04-13lib: sbi_trap: Add support for vectored interruptsSamuel Holland2-2/+4
When redirecting an exception to S-mode, transform the (v)stvec CSR value as described in the privileged spec to derive the S-mode PC. Since OpenSBI never redirects interrupts, only synchronous exceptions, the only action needed is to mask out the (v)stvec.MODE field. Reported-by: Jan Reinhard <jan.reinhard@sysgo.com> Closes: https://github.com/riscv-software-src/opensbi/issues/391 Signed-off-by: Samuel Holland <samuel.holland@sifive.com> Reviwed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250305014729.3143535-1-samuel.holland@sifive.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-03-28lib: Emit lr and sc instructions based on -march flagsChao-ying Fu5-1/+93
When -march=rv64im_zalrsc_zicsr is used, provide atomic operations and locks using lr and sc instructions only. Signed-off-by: Chao-ying Fu <cfu@mips.com> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250226014727.19710-1-cfu@mips.com Signed-off-by: Anup Patel <anup@brainfault.org>
2025-03-27lib: utils/serial: Add PXA UARTs supportJunhui Liu6-8/+24
The PXA variant of the uart8250 adds the UART Unit Enable bit (UUE) that needs to be set to enable the XScale PXA UART. And it is required for some RISC-V SoCs like the Spacemit K1 that implement the PXA UART. This introduces the "intel,xscale-uart" compatible to handle setting the UUE bit. Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Anup Patel <anup@brainfault.org> Link: https://lore.kernel.org/r/20250327-pxa-uart-support-v2-1-c4400c1fcd0b@pigmoral.tech Signed-off-by: Anup Patel <anup@brainfault.org>
2025-03-27lib: sbi: sse: Add support for SSTATUS.SDTClément Léger3-3/+13
Similarly to what is done for SPELP, handle SSTATUS.SDT upon event injection. In order to mimick an interrupt, set SDT to 1 for injection and save its previous value in interrupted_flags[5:5]. Restore it upon completion. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-27lib: sbi: sse: Add support for SSTATUS.SPELPClément Léger2-3/+14
As raised during the ARC review, SPELP was not handled during the event injection process. Save it as part of the interrupted flags, clear it before injecting the event and restore it after completion. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-27lib: sbi: sse: Remove superfluous parenthesis around MSTATUS_* valuesClément Léger1-2/+2
For some reason, there was a pair of useless parenthesis around MSTATUS_* value usage. Remove them. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-27lib: sbi: sse: Rename STATUS* interrupted flags to SSTATUS*Clément Léger2-8/+8
As raised by Andrew on the kvm-unit-test review, this flags are meant to hold SSTATUS bits in the specification. Rename them to match that. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
2025-03-27lib: sbi: sse: Return SBI_EDENIED for read only parameters.Clément Léger1-2/+8
The SSE specification did specified that read only parameters should return SBI_EBADRANGE but was modified recently to return SBI_EDENIED. Signed-off-by: Clément Léger <cleger@rivosinc.com> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
generated by cgit v1.1 at 2025-09-20 20:44:57 +0000