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Newer versions of gcc fail to compile OpenBIOS giving a
"error: ‘multiboot_header’ defined but not used" message when the default
build with -Werror enabled is used.
Remove the static declaration to enable compilation to succeed, which
incidentally matches the other copies of multiboot.c in the OpenBIOS
source tree.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Commit 0d3345f9 "pci: add ob_pci_unmap() to unmap PCI memory" accidentally
broke compilation for architectures where OFMEM is unavailable such as x86.
Add the appropriate #if defined(CONFIG_OFMEM)...#endif block to ob_pci_unmap()
so that compilation can at least succeed for these architectures.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This brings the device tree in agreement with a real Ultra 5.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This is because some OSs (noticeably NetBSD) look up devices by device_type
in order to establish an interrupt mapping.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Fix up the ebus device interrupt parents, plus remove deprecated code for
mapping PCI devices to the PCI root bus as this is no longer possible.
Now that the transition to a simba configuration is complete, make sure
that we update mem_base and io_base to match the start address of each
simba module, and update pci_mem_base accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Make sure that we set the upper 16-bits of the IO address for both the
PCI IO base and PCI IO limit registers.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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The IEEE-1275 interpose specification suggests that interposed packages should
not be visible unless an interpose-aware Forth word is used.
Commit 247c6169 "Fix for interpose problem" realised this by converting the romvec
obp_inst2pkg() function over to use ihandle>non-interposed-phandle but didn't make
the same change to the equivalent CIF call instance-to-path (which is presumably
correct since the interpose specification also states that interposed packages are
only visible to a new instance-to-interposed-path CIF call).
Here we add a new instance-to-package word as a wrapper to
ihandle>non-interposed-phandle and update obp_inst2pkg() and instance-to-path to
use it accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This can now be used in sungem_config_cb() to unmap the PCI BAR
used to configure the MAC address.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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No driver, but we read the MAC address from the chip and write
it into the device-tree where Linux and MacOS look for it. We
also set the right compatible property for MacOS to pick it up.
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This is so that it can be called directly from C rather than just the
pci-map-in Forth binding.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This is in anticipation of using in several other places.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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PCI bus B
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@iande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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The current interrupt mapping is only correct for PCI bus A (QEMU
currently alters its PCI mappings to handle that PCI devices are
plugged into the PCI root bus and not behind a Simba bridge).
Add a comment to point out that the existing mapping is deprecated
and should be removed once the QEMU PCI topology has been updated.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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The SUN,simba device doesn't have a ranges properties and so Linux will
calculate the PCI memory/IO ranges by probing the PBM "Memory Address Map"
and "I/O Address Map" registers (see apb_fake_ranges()).
Set sensible default values for both SUNW,simba devices during PCI
configuration and document accordingly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Sabre has a slightly different reg property than that of other PCI host
bridges. Hardcode the correct value as taken from a real Ultra 5 device
tree.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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The sabre on-board devices are located at devfn (1,1) which means that in a
standard PCI bus scan the bus at devfn (1, 0) is enumerated first. This
doesn't play well with OpenBIOS which assumes that the ebus (with legacy
ioports) is mapped starting from io_base == 0x0.
Perform a custom scan to ensure that OpenBIOS doesn't crash when additional
devices are added to the bus at devfn (1, 0).
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Make the PCI configuration space size match that of a real Ultra5 machine.
Currently the declared PCI configuration space is too large and actually
overlaps PCI memory space.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Previously the address of the PCI memory base in the host ranges property was
offset by pci_mem_base. While technically correct, Linux incorrectly calculates
the start of the Simba window based upon this address.
Change the memory base to APB_MEM_BASE to match a real Ultra 5 which prevents
Linux from outputting warnings about incorrect window sizes.
Signed-off-by: Mark Cave-ayland <mark.cave-ayland@ilande.co.uk>
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This is required to ensure that we can fit both SUNW,simba devices within
the available space.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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On a real machine the PCI memory space should be 10 times as large, however that
takes us to a 64-bit value which isn't directly supported by OpenBIOS. Increase
the PCI memory space by an amount which allows Linux to allocate the IOMMU correctly.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This is now handled by the host_ranges property so remove all remaining
references.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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As derived from the current logic in pci_host_set_ranges().
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Split the keyboard device into an 8042 controller device and a child keyboard
device as indicated in some SPARC and PReP device trees.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This allows the PS/2 keyboard device to be detected and used under *BSD
for SPARC64.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Always use devfn 0 for PCI host bridge ranges, regardless of the devfn of the
bridge itself. This generates a PCI host bridge ranges property matching that
of real hardware for PPC machines.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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The FreeBSD PPC bootloader attempts to reset the console causing an error
because the MMIO registers are already mapped. Add a check to ensure that
we only map them once.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Commit c80a58b added a workaround to allow ioport access through the first PCI
bridge found until its base and limits were programmed, so that on-board devices
not directly attached to the PCI host bus could be used during OpenBIOS
initialisation.
Unfortunately the logic was broken, and in fact the reset should only occur if
we're the first PCI bridge that isn't the host bridge - otherwise we end up
resetting io_base for the PCI host bus causing its devices to be mapped over
existing in-built ioports causing strange behaviour.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This serves 2 purposes: firstly it means that each PCI bridge can set its
own custom interrupt-map and interrupt-mask if required, and secondly the
interrupt properties can be split into per-architecure sections.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This is to allow us to generate interrupt maps for any PCI bus, not just the
PCI host bridge.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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As indicated by the IEEE-1275 PCI bindings, PCI-PCI bridges should call
call the map-in method of the parent.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This is in preparation for separating out the behaviour between host bridges
and PCI bridges.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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These two types of node will need to have slightly differing behaviours moving
forwards.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Instead of hard-coding the bus id to 0, grab the bus id from the first word
of the "bus-range" property. In particular this allows us to correctly
navigate the DT when trying to access a node with a unit id.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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This enables the bridge (and also any children) to determine their bus number
during the secondary PCI bus scan.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Currently the driver works by using the legacy VGA ioports for programming
the display. However this makes it much harder to configure e.g. multiple
displays or VGA devices behind multiple PCI bridges.
If building for QEMU, default to using the QEMU PCI MMIO registers to program
the display.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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These are particularly useful when accessing hardware registers from BE hosts.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Commit 7130437 "fw_cfg: implement fw-cfg-read-file Forth word" added a binding
for the Forth version of fw_cfg_read_file() into libopenbios/init.c but forgot
to only include the binding when CONFIG_DRIVER_FW_CFG was defined.
This broke the build for platforms which don't have the fw_cfg interface
enabled by default such as x86.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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If the fw_cfg interface provides a MacOS VGA PPC NDRV binary driver then
install it into the "driver,AAPL,MacOS,PowerPC" property of the QEMU VGA
package.
The installation of the binary is configured via the NVRAM configuration
variable "vga-ndrv?" (which is set to true by default for PPC) and also the
presence of the NDRV binary driver file within the QEMU fw_cfg interface
itself.
Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
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